对寄存器配置的编程方法

struct register_element CODEC_INIT_MIC1_LOUTR_REG[] = 
{
	//power down
	{0x810004,0x00}, //
	
	//assign syncdomain
	{0x810068,0x00}, //SDAIF1=SD1, SDAIF2=SD2
	{0x810069,0x30}, //SDAIF3=SD3, SDAIF4=SD4
	{0x81006A,0x03}, //ADC CODEC=3
	
//	{0x81006B,0x33}, //
//	{0x81006C,0x33}, //
//	{0x81006D,0x33}, //
//	{0x81006E,0x33}, //
//	{0x81006F,0x33}, //
	
	
#if 0
	//pll1 setting
	{0x81003E,0x05}, //XTI 26MHz
	{0x81003F,0x00}, //PLD1
	{0x810040,0x06}, //PLD1 D+1=7
	{0x810041,0x00}, //PLM1
	{0x810042,55-1}, //PLM1 M+1=39
	
	//clock setting
//	{0x810048,0x21}, //MCLK1=PLLCLK1 & Master mode
//	{0x810049,0x4F},//MBCLK1 divider {0x810049,0x4f}, //32fs=1536KHZ//{0x810049,0x27}, //BDV1+1=40 / CKS1/(BDV+1) / 64fs=3072kHz
//	{0x81004A,0x1F},//MSYNC1 divider {0x81004A,0x1f}, //fs=48kHZ //{0x81004A,0x3F}, //SDV1+1=64 / BCLK/(SDV+1) / fs=48kHz

	//Added by huberg 
	{0x81004e, 0x21},//MCLK3 = PLL1, master mode
	{0x81004f, 133-1},//BCLK3 = MCLK3/(79+1)
	{0x810050, 0x1F},//WCLK3 = BCLK3/(31+1)

	
	
	{0x810064,0x01},//CODEC Clock Source=PLLCLK1
	{0x810065,0x09},//CODEC MCLK  divider MDIV2+1=10
	{0x810066,0x01},//DSP MCLK=PLLCLK1
	{0x810067,0x09},//MCLK DIVD+1=10 BUS CLK DIV/

#else
	//pll1 setting
	{0x81003E,0x05}, //XTI 26MHz
	{0x81003F,0x00}, //PLD1
	{0x810040,0x07}, //PLD1 D+1=7
	{0x810041,0x00}, //PLM1
	{0x810042,40-1}, //PLM1 M+1=39
	
	//clock setting
//	{0x810048,0x21}, //MCLK1=PLLCLK1 & Master mode
//	{0x810049,0x4F},//MBCLK1 divider {0x810049,0x4f}, //32fs=1536KHZ//{0x810049,0x27}, //BDV1+1=40 / CKS1/(BDV+1) / 64fs=3072kHz
//	{0x81004A,0x1F},//MSYNC1 divider {0x81004A,0x1f}, //fs=48kHZ //{0x81004A,0x3F}, //SDV1+1=64 / BCLK/(SDV+1) / fs=48kHz

	//Added by huberg 
	{0x81004e, 0x21},//MCLK3 = PLL1, master mode
	{0x81004f, 80-1},//BCLK3 = MCLK3/(79+1)
	{0x810050, 0x1F},//WCLK3 = BCLK3/(31+1)

	
	
	{0x810064,0x01},//CODEC Clock Source=PLLCLK1
	{0x810065,0x09},//CODEC MCLK  divider MDIV2+1=10
	{0x810066,0x01},//DSP MCLK=PLLCLK1
	{0x810067,0x09},//MCLK DIVD+1=10 BUS CLK DIV/
#endif


	
	//Added by huberg
	{0x810098, 0x00},//DSPCKADJ = 0, DSPMCLK = DSPMCLK source*(256-DSPCKADJ)/256
//I2S
	//codec
	//changed by Huberg
	{0x810006,0x0F}, //All on 
	
	
	//{0x810006,0x03}, //PMMP1A PMMP1B=ON
	{0x81001A,0x0a}, //fs=48kHz, CODEC Master Clock=256fs
	{0x810020,0x21}, //DAC1R=Rch,DAC1L=Lch@Mixing
	{0x810021,0x21}, //DAC2R=Rch,DAC2L=Lch
	
	//Added by huberg
	//{0x81002e, 0x40},//dac clock
	
	//{0x81000d,0x01}, //full defferential mode
	
	
	
	{0x81008B, 0x01},//I2S  16bit	
	{0x81008D, 0x01},//digital IF3 I2S mode
	{0x81008F, 0x01},//codec DIF 16bit IIS
	///DMIC/
	
	#if (STATION_ID==SBC_STATION)
	{0x81001E,0x1B}, //ADC1 Digital MIcrophone Connection Select£ºDMIC1
	#elif (STATION_ID==SPIDER_STATION)
	{0x81001F,0x1B}, //ADC2 Digital MIcrophone Connection Select£ºDMIC2
	#endif

//{0x81003C,0x77}, //Lineout 2=-4dB
	
	//path
	{0x810079,0x06}, //DAC1   <= SDTI3
	{0x81007A,0x06}, //DAC2   <= SDTI3
	
	#if (STATION_ID==SBC_STATION)
	{0x810075,0x09}, //SDTO3   <= ADC1
	#elif (STATION_ID==SPIDER_STATION)
	{0x810075,0x0A}, //SDTO3   <= ADC2
	#endif

	
	//power up
	{0x810003,0x03},//PLL1&2 power up
	{0x810003,0x13},//Xtal power up
	{0x810000,0x01},// Power Switch of DSP, SRCA/B/C/D and SRAM blocks
	{0x810000,0x03},//Logic reset of DSP, SRCA/B/C/D and SRAM blocks
	{0x810005,0x05},
	{0x810005,0xD5},
	{0x810005,0xD7},
	{0x81000A,0x85},//power DAC1 and DAC2    
	{0x81000B,0x03},//power HP(headphone)
	{0x81000c,0x33},//power linout 2

	{0x81000F,0x0A},//MPWR2/1C/1B/1A :1V8
	
	
	{0x810007,0x01},//AIN1 
//	{0x810008,0x03},//power ADC1 
//	{0x810008,0x0C},//power ADC2	
	{0x810008,0x0F},//power ADC1 and ADC2
	{0x810004,0x1F},//
};

struct register_element
{
    uint32_t address;
    uint32_t data;
};

HAL_StatusTypeDef AK4961_REG_MIC1_LOUTR_Init(void)
{
	uint8_t i = 0;
	
	for(i = 0; i < (sizeof(CODEC_INIT_MIC1_LOUTR_REG))/(sizeof(struct register_element)); i++)
	{
		if(AK4961WriteReg(CODEC_INIT_MIC1_LOUTR_REG[i].address,CODEC_INIT_MIC1_LOUTR_REG[i].data) != HAL_OK)
		{
			return HAL_ERROR;
		}
		delay_ms(20);
	}	
	return HAL_OK;
}

原来还可以这样配置寄存器，学习一下