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原创 平行编程技术让FPGA开发易如反掌
目前,谈到FPGA开发很多人还是认为这是牵涉硬件IC设计的开发,其难度相当大,不过,这个想法恐怕在2010年要得到彻底颠覆了,“我们在和AutoESL公司合作推出C to FPGA平行编程技术,采用这个技术后,只要用C语言开发出代码,用AutoESL的编译器可以直接生成FPGA可用的代码,这会大大降低FPGA的开发门槛。”张宇清透露,“BDTI通过测试发现,用AutoESL公司生成的代码和用D
2010-05-26 17:47:00 535
原创 BDTI certifies AutoESL : AutoPilot
BDTI Certified™ Results for the AutoESL AutoPilot High-Level Synthesis ToolUsed in Conjunction with a Xilinx Spartan-3A DSP 3400 FPGA and the Xilinx ISE and EDK ToolsAbout AutoESL AutoPilot
2010-05-26 16:05:00 510
原创 AutoESL AutoPilot : Customers
CustomersAutoESL’s high level synthesis tool has been adopted by some of the world’s largest software and semi-conductor companies. Our customers have developed products in multiple application do
2010-05-26 16:02:00 813
原创 AutoESL AutoPilot : Applications
ApplicationsAutoPilot’s powerful high level synthesis has been used on designs in multiple application domains. It showcases the flexibility of the tool to handle a variety of design styles and a
2010-05-26 15:57:00 418
转载 Is it time to start using high-level synthesis?
http://blogs.cancom.com/elogic_920000692/2010/04/30/is-it-time-to-start-using-high-level-synthesis/ One big question people have about high-level synthesis (HLS) is whether or not it is ready fo
2010-05-26 15:54:00 535 1
转载 你还在用HDL语言进行设计吗?
手写RTL的后果是仿真时间长,叠代次数多,bug难寻找,结果就是一个芯片不断的仿真,respin. 业界已经宣称RTL不适宜于大规模的电路设计,很多语言工具不断推出,就是所谓的ESL设计,高级综合,设计语言涉及到systemc,systemverilog,pure c, 类c语言,另类语言. systemc: http://www.bluespec.com ESE http
2010-05-26 14:53:00 780
原创 High-level Synthesis Vendors
PICO from SynforaAutoPilot from AutoESLC-to-Silicon from Cadence Design SystemsSynphony HLS from SynopsysPowerOpt from ChipVisionCynthesizer from Forte Design SystemsCatapult C from M
2010-05-26 14:44:00 850
原创 VGA(DVI interface) Controller的高层次综合
// Genarate synch signal to drive DVI output, here 720P is as defaultvoid vga_ctrl(volatile int24 *velXY, volatile uint8 *frameY, struct dvi_video *dvi_o, volatile uint1 *sync_enable){ uint12 hcoun
2010-05-26 14:28:00 507
原创 基本运算单元的高层次综合:C/C++ to RTL
本文以加法为例:[code]//----------------------------------------------------//adder.c//---------------------------------------------------void adder(int a, int b, int *sum){ *sum = a + b;}[/code][size=
2010-05-26 14:27:00 782
转载 Can C beat RTL?
http://www.edn.com/article/457428-Can_C_beat_RTL_.php With the appearance of higher speeds and more DSP macrocells in low-cost FPGAs, more and more design teams are seeing the configurable chip
2010-05-26 14:22:00 334
转载 实际使用高层次综合(HLS)的时机是否成熟?
人们对高层次综合(HLS)有一个很大的疑问就是它是否已经成为主流使用。换句话说,它是已经主流了还是没有?HLS有历史悠久产品,比如从来没有获得足够重视的Synopsys的行为编译器和Cadence的视觉设计师。然后是下一代产品,Synfora,Forte和Mentor的CatapultC。最近还AutoESL的AutoPilot和Cadence的CtoSilicon。 阿图尔,AutoESL
2010-05-26 14:03:00 1168
转载 GNU gprof
http://www.cs.utah.edu/dept/old/texinfo/as/gprof.htmlGNU gprofThis manual describes the GNU profiler, gprof, and how you can use it to determine which parts of a program are taking most of the
2010-05-17 10:23:00 578
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