VHDL语法学习笔记

1/
   port's direction:
<               in
>               out
>               inout
>               buffer
>               linkage      (no confirmed direction, can link with any direction's signal.)

2/
   data type:
>        there's 10 typies of a data.but always use this one:
>               bit  (can be '1' or '0') and this type often be declared in 'std_logic' and 'std_logic_vector'
>              

3/
    block  usage:
>       [blockname]:
>        block
>        begin
>               .......
>        end block [blockname];
[ftc=#F68E54]block is a structure of VHDL expressions in block are collateral,which are different from process [/ft]

4/
   subprogram
>      there are two kinds of subprogram: function and procedure.And their usage:
>            function [function name] (<argument list>) is
>               return  [data name] is
>               [declaring expressiong]
>            begin
>               [access expression];
>                return [variable name];
>            end [function name];
>       ---------------------------------------------------------
>            procedure [procedure name] (<arguement list>) is
>            begin
>                [access expression];
>            end [procedure name];
And something should be noted is  [ftc=#F68E54]Expressions in function and procedure are ordinal  accessed[/ft]

5/
   package usage:
>      package [package name] is
>          {construction expression];
>      end [package name];
>      package body [package name] is
>                [construction statement];
>      end body;
[B] So you see , package's usage somewhat like Entity,but a little different: there isn't an 'of' in before 'is'.[/B]
[ftc=#f68e54]package is used to list out signals,constant,datatype,component,function,procedure 's defintion.Which ate exprected to be used.[/ft]

6/
   configuration
>     configuration [configuration name] of [entity name] is
>           [construction statement];
>     end [configuration name];
>     configuration [configuration name] of [entity name] is
?         for [config architecture name]
>        end for;
>      end [configuration name];
[ftc=#F597e9] this configuration didn't include block and component.and use to link different level's entity structure.[/ft]

7/
   custom datatype
      a.type usage:
             1) type [typename] is [type construction] of [base datatype];
             2) type [typename] is (enumerate list];

8/
type [array name] is array ([area]) of data type;
type [array name] is array ([flag type] range<>);
    example: type bit_vector is array(natural range<>);
  variable var : bit_vector(0 to 1);

to_stdlogicvecter(a);    change a from bit_vector to std_logic_vector.
to_bitvector(a); change a fron std_logic_vector to bit_vector.
to_stdlogic(a);
to_bit(a);

[ftc=#f68e54]this four functions are includeed in std_logic_1164 package.[/ft]

9/
  wait.
            wait ;
                     wait on [signal list];
                     wait for [time];
                     wait until [condition expession];
10/
 loop
                     example:
                        l2: loop
                          a:=a+1;
                           exit l2 when a>10;
                           end loop l2;
 and it's meaning is obvious.

11/
 while loop
                            [ loop flag:] ehile <condition> loop
                                <ordinal statement>
                                   end loop [loop flag];