ARM Generic Interrupt COntroler (GIC)-Distribution and Routing

翻译 2016年08月31日 15:50:03

Distributer and Redistributor

  • Distributer:
    • provide routinbg config for SPIs and SGIs
    • hold associated routing and priority info
    • GICD_CTLR控制global setting
      • enable affinity routing
      • disable security
      • enable secure and non-secure Group1 Interrupt
      • enable Group0 Interrupt
    • 提供给SPI的编程接口
      • enable/disable SPIs
      • 设置SPI的priority
      • SIP routing info
      • 设置SPI是level-sensitive或者edge-sensitive
      • 生成message-based SPI
      • assign each SPI to an Interrupt Group
      • 控制SPI state:pending or active
    • 对于legacy operation,Distributor控制PPI和SGI的config
  • Redistributor
    • 连接在CPU interface上,provide config settings for PPIs and SGIs
    • 保留control,priority和pending info for all physical LIPs(内存中)
      • 使用寄存器:GICR_PROPBASER和GICR_PENDBASER
      • direct injection: GICV4中,redistributor负责virtual LPIs by ITS to redistributor和directly to VM,不需要hypervisor介入;
        • 同样收集virtual LPI的各类info,使用寄存器GICR_VPROPBASER和GICR_VPENDBASER
        • 如果支持LPI但没有ITS,GICR_*寄存器需要包含一个memory-mapped interface来控制physical LPIs
    • Redistributor提供的编程接口有:
      • identify,control,config to enable Interrupt and routing info
      • enable/disable SGI和PPI
      • 设置SGI和PPI的priority level
      • 支持 PPI to level-sensitive或edge-sensitive
      • assign SGI或PPI to Interrupt Group
      • control stateL: pending or active
      • power management
      • base addr control for LPIs或vertial Interrupt
    • a Redistributor Always presents the pending interrupts with the highers priority to CPU in finite time.
  • ITS: Interrupt translation service
    • optional in v3,route LPI to redistributor
    • 软件通过一个command queue来配置ITS,通过内存中的表将Device对应的EventID转换成PE对应的pending INTID
  • highest priority pending interrupts might change
    • The previous highest priority interrupt has been acknowledged.
    • The previous highest priority interrupt has been preempted.、The previous highest
    • priority interrupt is removed and no longer valid.
    • The group interrupt enable has been modified.
    • The PE is no longer a participating PE.

CPU interface

  • each cpu interface提供的programming接口有:
    • general control and config of Interrupt handling
    • acknowledge interrupt
    • priority drop
    • deactivate Interrupt
    • 设置PE的Interrupt priority mask
    • 定义PE的preemption policy
    • 定义PE highest priority pending Interrupt
  • CPU interface包括
    • component允许supervisory software控制physical interrupt。使用寄存器ICC_*
    • component允许控制virtual Interrupt使用寄存器ICV_*
    • component允许hypervisor控制pending Interrupt。使用寄存器ICH_*

INTIDs

  • INTIDs: Interrupt ID numbers
  • INTID is RAS, means Zero-extended
  • INTID supported in DIstributor and Redistributor:
    • if LPIs not supported, ID of Distributor is limited to 10 bits (Forward Compatible)
    • if LPIs supported, ID is 14~24 bits, defined in GICD_TYPER
    • Redistributor ID fewer than Distributor, defined in GICR_PROPBASER
  • INTID supported in ITS:
    • if LPIs supported, ID is 14~24 bits, defined in GITS_TYPOER.ID
    • ITS只能fwd Redistributor ID range内的Interrupt, 否则unpredictable
  • INTID supported in CPU interface
    • GICv3 support 16 or 23 bits INTID field。defined in ICC_CTRL_EL1.ID and ICC_CTRL_EL2.ID
    • fwd给CPU端大于其ID range的INTID会产生programming error
  • INTD具体对应表: GIC section 2.2 Table2-1, 2-2

Affinity Routing

  • a hierarchical address-based interrupt routing
  • defination:
    • AArch64: MPIDR_EL1;
    • AArch32: MPIDR
  • 32 bits, 4个8bits affinity fields: a,b,c,d
    • AArch64 使用ICC_CTRL_EL3.A3V, ICC_CTRL_EL1.A3V和GICD_TYPER.A3V配置3个还是4个
    • AArch64 support 4;AArch32 support 3
  • Affinity enable:
    • Secure interrupts, GICD_CTRL.ARE_S = 1 (Affinity Routing Enable)
    • Non-secure interrupts, GICD_CTRL.ARE_NS = 1
  • SPIs affinity routing: see GIC section 2.3.1
  • SGIs affinity routing: see GIC section 2.3.1
  • participating nodes see GIC section 2.3.2
  • changing affinity routing enables see GIC section 2.3.3

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