ARM平台下独占访问指令LDREX和STREX的原理与使用详解

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为了实现线程间同步,一般都要在执行关键代码段之前加互斥(Mutex)锁,且在执行完关键代码段之后解锁。为了实现所谓的互斥锁的概念,一般都需要所在平台提供支持。

在计算机领域里,如果要在多线程的情况下要保持数据的同步,需要引入称作Load-Link(LL)和Store-Conditional(SC)的操作,通常简称为LL/SC。LL操作返回一个内存地址上当前存储的值,后面的SC操作,会向这个内存地址写入一个新值,但是只有在这个内存地址上存储的值,从上个LL操作开始直到现在都没有发生改变的情况下,写入操作才能成功,否则都会失败。这个操作非常重要,是很多平台实现基本原子操作的基础。 对于ARM平台来说,也在硬件层面上提供了对LL/SC的支持,LL操作用的是LDREX指令,SC操作用的是STREX指令。

本文主要用来说明ARM平台上特有的独占访问指令LDREX和STREX的工作原理,以及如何使用。而它们也是ARM平台上,实现互斥锁等线程同步工具的基础。

我们先来看看LDREX和STREX两条指令的语义。其实LDREX和STREX指令,是将单纯的更新内存的原子操作分成了两个独立的步骤。

1)LDREX用来读取内存中的值,并标记对该段内存的独占访问:

LDREX Rx, [Ry]

上面的指令意味着,读取寄存器Ry指向的4字节内存值,将其保存到Rx寄存器中,同时标记对Ry指向内存区域的独占访问。

如果执行LDREX指令的时候发现已经被标记为独占访问了,并不会对指令的执行产生影响。

2)而STREX在更新内存数值时,会检查该段内存是否已经被标记为独占访问,并以此来决定是否更新内存中的值:

STREX Rx, Ry, [Rz]

如果执行这条指令的时候发现已经被标记为独占访问了,则将寄存器Ry中的值更新到寄存器Rz指向的内存,并将寄存器Rx设置成0。指令执行成功后,会将独占访问标记位清除。

而如果执行这条指令的时候发现没有设置独占标记,则不会更新内存,且将寄存器Rx的值设置成1。

一旦某条STREX指令执行成功后,以后再对同一段内存尝试使用STREX指令更新的时候,会发现独占标记已经被清空了,就不能再更新了,从而实现独占访问的机制。

大致的流程就是这样,但是ARM内部为了实现这个功能,还有不少复杂的情况要处理。

在ARM系统中,内存有两种不同且对立的属性,即共享(Shareable)和非共享(Non-shareable)。共享意味着该段内存可以被系统中不同处理器访问到,这些处理器可以是同构的也可以是异构的。而非共享,则相反,意味着该段内存只能被系统中的一个处理器所访问到,对别的处理器来说不可见。

为了实现独占访问,ARM系统中还特别提供了所谓独占监视器(Exclusive Monitor)的东西,其结构大致如下:

可以看出来,一共有两种类型的独占监视器。每一个处理器内部都有一个本地监视器(Local Monitor),且在整个系统范围内还有一个全局监视器(Global Monitor)。

如果要对非共享内存区中的值进行独占访问,只需要涉及本处理器内部的本地监视器就可以了;而如果要对共享内存区中的内存进行独占访问,除了要涉及到本处理器内部的本地监视器外,由于该内存区域可以被系统中所有处理器访问到,因此还必须要由全局监视器来协调。

对于本地监视器来说,它只标记了本处理器对某段内存的独占访问,在调用LDREX指令时设置独占访问标志,在调用STREX指令时清除独占访问标志。

而对于全局监视器来说,它可以标记每个处理器对某段内存的独占访问。也就是说,当一个处理器调用LDREX访问某段共享内存时,全局监视器只会设置针对该处理器的独占访问标记,不会影响到其它的处理器。当在以下两种情况下,会清除某个处理器的独占访问标记:

1)当该处理器调用LDREX指令,申请独占访问另一段内存时;

2)当别的处理器成功更新了该段独占访问内存值时。

对于第二种情况,也就是说,当独占内存访问内存的值在任何情况下,被任何一个处理器更改过之后,所有申请独占该段内存的处理器的独占标记都会被清空。

另外,更新内存的操作不一定非要是STREX指令,任何其它存储指令都可以。但如果不是STREX的话,则没法保证独占访问性。

现在的处理器基本上都是多核的,一个芯片上集成了多个处理器。而且对于一般的操作系统,系统内存基本上都被设置上了共享属性,也就是说对系统中所有处理器可见。因此,我们这里主要分析多核系统中对共享内存的独占访问的情况。

为了更加清楚的说明,我们可以举一个例子。假设系统中有两个处理器内核,而一个程序由三个线程组成,其中两个线程被分配到了第一个处理器上,另外一个线程被分配到了第二个处理器上。且他们的执行序列如下:

大致经历的步骤如下:

1)CPU2上的线程3最早执行LDREX,锁定某段共享内存区域。它会相应更新本地监视器和全局监视器。

2)然后,CPU1上的线程1执行LDREX,它也会更新本地监视器和全局监视器。这时在全局监视器上,CPU1和CPU2都对该段内存做了独占标记。

3)接着,CPU1上的线程2执行LDREX指令,它会发现本处理器的本地监视器对该段内存有了独占标记,同时全局监视器上CPU1也对该段内存做了独占标记,但这并不会影响这条指令的操作。

4)再下来,CPU1上的线程1最先执行了STREX指令,尝试更新该段内存的值。它会发现本地监视器对该段内存是有独占标记的,而全局监视器上CPU1也有该段内存的独占标记,则更新内存值成功。同时,清除本地监视器对该段内存的独占标记,还有全局监视器所有处理器对该段内存的独占标记。

5)下面,CPU2上的线程3执行STREX指令,也想更新该段内存值。它会发现本地监视器拥有对该段内存的独占标记,但是在全局监视器上CPU1没有了该段内存的独占标记(前面一步清空了),则更新不成功。

6)最后,CPU1上的线程2执行STREX指令,试着更新该段内存值。它会发现本地监视器已经没有了对该段内存的独占标记(第4步清除了),则直接更新失败,不需要再查全局监视器了。

所以,可以看出来,这套机制的精髓就是,无论有多少个处理器,有多少个地方会申请对同一个内存段进行操作,保证只有最早的更新可以成功,这之后的更新都会失败。失败了就证明对该段内存有访问冲突了。实际的使用中,可以重新用LDREX读取该段内存中保存的最新值,再处理一次,再尝试保存,直到成功为止。

还有一点需要说明,LDREX和STREX是对内存中的一个字(Word,32 bit)进行独占访问的指令。如果想独占访问的内存区域不是一个字,还有其它的指令:

1)LDREXB和STREXB:对内存中的一个字节(Byte,8 bit)进行独占访问;

2)LDREXH和STREXH:中的一个半字(Half Word,16 bit)进行独占访问;

3)LDREXD和STREXD:中的一个双字(Double Word,64 bit)进行独占访问。

它们必须配对使用,不能混用。

在ARMv8指令集下,LDREX指令被改名成了LDXR指令,而STREX指令被改名成了STXR指令,功能基本上是一样的,除了添加了一个新的特性。当全局监视器标记的对某段内存的独占访问被清空后,将向所有标记了对该段内存独占访问的CPU核都发送事件,将它们从WFE指令中唤醒,继续执行。

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Table of Contents Preface About this book Using this book Glossary Typographic conventions Feedback Other information 1 Overview of the Assembler 1.1 About the ARM Compiler toolchain assemblers 1.2 Key features of the assembler 1.3 How the assembler works 1.4 Directives that can be omitted in pass 2 of the assembler 2 Overview of the ARM Architecture 2.1 About the ARM architecture 2.2 ARM, Thumb, and ThumbEE instruction sets 2.3 Changing between ARM, Thumb, and ThumbEE state 2.4 Processor modes, and privileged and unprivileged software execution 2.5 Processor modes in ARMv6-M and ARMv7-M 2.6 VFP hardware 2.7 ARM registers 2.8 General-purpose registers 2.9 Register accesses 2.10 Predeclared core register names 2.11 Predeclared extension register names 2.12 Predeclared coprocessor names 2.13 Program Counter 2.14 Application Program Status Register 2.15 The Q flag 2.16 Current Program Status Register 2.17 Saved Program Status Registers 2.18 ARM and Thumb instruction set overview 2.19 Access to the inline barrel shifter 3 Structure of Assembly Language Modules 3.1 Syntax of source lines in assembly language 3.2 Literals 3.3 ELF sections and the AREA directive 3.4 An example ARM assembly language module 4 Writing ARM Assembly Language 4.1 About the Unified Assembler Language 4.2 Register usage in subroutine calls 4.3 Load immediate values 4.4 Load immediate values using MOV and MVN 4.5 Load immediate values using MOV32 4.6 Load immediate values using LDR Rd, =const 4.7 Literal pools 4.8 Load addresses into registers 4.9 Load addresses to a register using ADR 4.10 Load addresses to a register using ADRL 4.11 Load addresses to a register using LDR Rd, =label 4.12 Other ways to load and store registers 4.13 Load and store multiple register instructions 4.14 Load and store multiple register instructions in ARM and Thumb 4.15 Stack implementation using LDM and STM 4.16 Stack operations for nested subroutines 4.17 Block copy with LDM and STM 4.18 Memory accesses 4.19 The Read-Modify-Write operation 4.20 Optional hash with immediate constants 4.21 Use of macros 4.22 Test-and-branch macro example 4.23 Unsigned integer division macro example 4.24 Instruction and directive relocations 4.25 Frame directives 4.26 Exception tables and Unwind tables 4.27 Assembly language changes after RVCT v2.1 5 Condition Codes 5.1 Conditional instructions 5.2 Conditional execution in ARM state 5.3 Conditional execution in Thumb state 5.4 Updates to the condition flags 5.5 Condition code suffixes and related flags 5.6 Comparison of condition code meanings in integer and floating-point code 5.7 Benefits of using conditional execution 5.8 Example showing the benefits of using conditional instructions 5.9 Optimization for execution speed 6 Using the Assembler 6.1 armasm command-line syntax 6.2 Specify command-line options with an environment variable 6.3 Using stdin to input source code to the assembler 6.4 Built-in variables and constants 6.5 Identifying versions of armasm in source code 6.6 Diagnostic messages 6.7 Interlocks diagnostics 6.8 Automatic IT block generation 6.9 Thumb branch target alignment 6.10 Thumb code size diagnostics 6.11 ARM and Thumb instruction portability diagnostics 6.12 Instruction width diagnostics 6.13 Two pass assembler diagnostics 6.14 Conditional assembly 6.15 Using the C preprocessor 6.16 Address alignment 6.17 Instruction width selection in Thumb 7 Symbols, Literals, Expressions, and Operators 7.1 Symbol naming rules 7.2 Variables 7.3 Numeric constants 7.4 Assembly time substitution of variables 7.5 Register-relative and PC-relative expressions 7.6 Labels 7.7 Labels for PC-relative addresses 7.8 Labels for register-relative addresses 7.9 Labels for absolute addresses 7.10 Numeric local labels 7.11 Syntax of numeric local labels 7.12 String expressions 7.13 String literals 7.14 Numeric expressions 7.15 Syntax of numeric literals 7.16 Syntax of floating-point literals 7.17 Logical expressions 7.18 Logical literals 7.19 Unary operators 7.20 Binary operators 7.21 Multiplicative operators 7.22 String manipulation operators 7.23 Shift operators 7.24 Addition, subtraction, and logical operators 7.25 Relational operators 7.26 Boolean operators 7.27 Operator precedence 7.28 Difference between operator precedence in assembly language and C 8 VFP Programming 8.1 Architecture support for VFP 8.2 Half-precision extension for VFP 8.3 Fused Multiply-Add extension for VFP 8.4 Extension register bank mapping in VFP 8.5 VFP views of the extension register bank 8.6 Load values to VFP registers 8.7 Conditional execution of VFP instructions 8.8 Floating-point exceptions in VFP 8.9 VFP data types 8.10 Extended notation extension for VFP 8.11 VFP system registers 8.12 Flush-to-zero mode 8.13 When to use flush-to-zero mode in VFP 8.14 The effects of using flush-to-zero mode in VFP 8.15 VFP operations not affected by flush-to-zero mode 8.16 VFP vector mode 8.17 Vectors in the VFP extension register bank 8.18 VFP vector wrap-around 8.19 VFP vector stride 8.20 Restriction on vector length 8.21 Control of scalar, vector, and mixed operations 8.22 Overview of VFP directives and vector notation 8.23 Pre-UAL VFP syntax and mnemonics 8.24 Vector notation 8.25 VFPASSERT SCALAR 8.26 VFPASSERT VECTOR 9 Assembler Command-line Options 9.1 --16 9.2 --32 9.3 --apcs=qualifier…qualifier 9.4 --arm 9.5 --arm_only 9.6 --bi 9.7 --bigend 9.8 --brief_diagnostics, --no_brief_diagnostics 9.9 --checkreglist 9.10 --compatible=name 9.11 --cpreproc 9.12 --cpreproc_opts=option[,option,…] 9.13 --cpu=list 9.14 --cpu=name 9.15 --debug 9.16 --depend=dependfile 9.17 --depend_format=string 9.18 --diag_error=tag[,tag,…] 9.19 --diag_remark=tag[,tag,…] 9.20 --diag_style={arm|ide|gnu} 9.21 --diag_suppress=tag[,tag,…] 9.22 --diag_warning=tag[,tag,…] 9.23 --dllexport_all 9.24 --dwarf2 9.25 --dwarf3 9.26 --errors=errorfile 9.27 --execstack, --no_execstack 9.28 --execute_only 9.29 --exceptions, --no_exceptions 9.30 --exceptions_unwind, --no_exceptions_unwind 9.31 --fpmode=model 9.32 --fpu=list 9.33 --fpu=name 9.34 -g 9.35 --help 9.36 -idir[,dir, …] 9.37 --keep 9.38 --length=n 9.39 --li 9.40 --library_type=lib 9.41 --liclinger=seconds 9.42 --licretry 9.43 --list=file 9.44 --list= 9.45 --littleend 9.46 -m 9.47 --maxcache=n 9.48 --md 9.49 --no_code_gen 9.50 --no_esc 9.51 --no_hide_all 9.52 --no_regs 9.53 --no_terse 9.54 --no_warn 9.55 -o filename 9.56 --pd 9.57 --predefine "directive" 9.58 --reduce_paths, --no_reduce_paths 9.59 --regnames 9.60 --report-if-not-wysiwyg 9.61 --show_cmdline 9.62 --split_ldm 9.63 --thumb 9.64 --thumbx 9.65 --unaligned_access, --no_unaligned_access 9.66 --unsafe 9.67 --untyped_local_labels 9.68 --version_number 9.69 --via=filename 9.70 --vsn 9.71 --width=n 9.72 --xref 10 ARM and Thumb Instructions 10.1 ARM and Thumb instruction summary 10.2 Instruction width specifiers 10.3 Flexible second operand (Operand2) 10.4 Syntax of Operand2 as a constant 10.5 Syntax of Operand2 as a register with optional shift 10.6 Shift operations 10.7 Saturating instructions 10.8 Condition code suffixes 10.9 ADC 10.10 ADD 10.11 ADR (PC-relative) 10.12 ADR (register-relative) 10.13 ADRL pseudo-instruction 10.14 AND 10.15 ASR 10.16 B 10.17 BFC 10.18 BFI 10.19 BIC 10.20 BKPT 10.21 BL 10.22 BLX 10.23 BX 10.24 BXJ 10.25 CBZ and CBNZ 10.26 CDP and CDP2 10.27 CLREX 10.28 CLZ 10.29 CMP and CMN 10.30 CPS 10.31 CPY pseudo-instruction 10.32 DBG 10.33 DMB 10.34 DSB 10.35 EOR 10.36 ERET 10.37 HVC 10.38 ISB 10.39 IT 10.40 LDC and LDC2 10.41 LDM 10.42 LDR (immediate offset) 10.43 LDR (PC-relative) 10.44 LDR (register offset) 10.45 LDR (register-relative) 10.46 LDR pseudo-instruction 10.47 LDR, unprivileged 10.48 LDREX 10.49 LSL 10.50 LSR 10.51 MCR and MCR2 10.52 MCRR and MCRR2 10.53 MLA 10.54 MLS 10.55 MOV 10.56 MOV32 pseudo-instruction 10.57 MOVT 10.58 MRC and MRC2 10.59 MRRC and MRRC2 10.60 MRS (PSR to general-purpose register) 10.61 MRS (system coprocessor register to ARM register) 10.62 MSR (ARM register to system coprocessor register) 10.63 MSR (general-purpose register to PSR) 10.64 MUL 10.65 MVN 10.66 NEG pseudo-instruction 10.67 NOP 10.68 ORN (Thumb only) 10.69 ORR 10.70 PKHBT and PKHTB 10.71 PLD and PLI 10.72 POP 10.73 PUSH 10.74 QADD 10.75 QADD8 10.76 QADD16 10.77 QASX 10.78 QDADD 10.79 QDSUB 10.80 QSAX 10.81 QSUB 10.82 QSUB8 10.83 QSUB16 10.84 RBIT 10.85 REV 10.86 REV16 10.87 REVSH 10.88 RFE 10.89 ROR 10.90 RRX 10.91 RSB 10.92 RSC 10.93 SADD8 10.94 SADD16 10.95 SASX 10.96 SBC 10.97 SBFX 10.98 SDIV 10.99 SEL 10.100 SETEND 10.101 SEV 10.102 SHADD8 10.103 SHADD16 10.104 SHASX 10.105 SHSAX 10.106 SHSUB8 10.107 SHSUB16 10.108 SMC 10.109 SMLAxy 10.110 SMLAD 10.111 SMLAL 10.112 SMLALD 10.113 SMLALxy 10.114 SMLAWy 10.115 SMLSD 10.116 SMLSLD 10.117 SMMLA 10.118 SMMLS 10.119 SMMUL 10.120 SMUAD 10.121 SMULxy 10.122 SMULL 10.123 SMULWy 10.124 SMUSD 10.125 SRS 10.126 SSAT 10.127 SSAT16 10.128 SSAX 10.129 SSUB8 10.130 SSUB16 10.131 STC and STC2 10.132 STM 10.133 STR (immediate offset) 10.134 STR (register offset) 10.135 STR, unprivileged 10.136 STREX 10.137 SUB 10.138 SUBS pc, lr 10.139 SVC 10.140 SWP and SWPB 10.141 SXTAB 10.142 SXTAB16 10.143 SXTAH 10.144 SXTB 10.145 SXTB16 10.146 SXTH 10.147 SYS 10.148 TBB and TBH 10.149 TEQ 10.150 TST 10.151 UADD8 10.152 UADD16 10.153 UASX 10.154 UBFX 10.155 UDIV 10.156 UHADD8 10.157 UHADD16 10.158 UHASX 10.159 UHSAX 10.160 UHSUB8 10.161 UHSUB16 10.162 UMAAL 10.163 UMLAL 10.164 UMULL 10.165 UND pseudo-instruction 10.166 UQADD8 10.167 UQADD16 10.168 UQASX 10.169 UQSAX 10.170 UQSUB8 10.171 UQSUB16 10.172 USAD8 10.173 USADA8 10.174 USAT 10.175 USAT16 10.176 USAX 10.177 USUB8 10.178 USUB16 10.179 UXTAB 10.180 UXTAB16 10.181 UXTAH 10.182 UXTB 10.183 UXTB16 10.184 UXTH 10.185 WFE 10.186 WFI 10.187 YIELD 11 VFP Instructions 11.1 Summary of VFP instructions 11.2 VABS (floating-point) 11.3 VADD (floating-point) 11.4 VCMP, VCMPE 11.5 VCVT (between single-precision and double-precision) 11.6 VCVT (between floating-point and integer) 11.7 VCVT (between floating-point and fixed-point) 11.8 VCVTB, VCVTT (half-precision extension) 11.9 VDIV 11.10 VFMA, VFMS, VFNMA, VFNMS (floating-point) 11.11 VLDM (floating-point) 11.12 VLDR (floating-point) 11.13 VLDR (post-increment and pre-decrement, floating-point) 11.14 VLDR pseudo-instruction 11.15 VMLA (floating-point) 11.16 VMLS (floating-point) 11.17 VMOV (floating-point) 11.18 VMOV (between one ARM register and single precision VFP) 11.19 VMOV (between two ARM registers and one or two extension registers) 11.20 VMOV (between an ARM register and half a double precision VFP register) 11.21 VMRS 11.22 VMSR 11.23 VMUL (floating-point) 11.24 VNEG (floating-point) 11.25 VNMLA (floating-point) 11.26 VNMLS (floating-point) 11.27 VNMUL (floating-point) 11.28 VPOP (floating-point) 11.29 VPUSH (floating-point) 11.30 VSQRT 11.31 VSTM (floating-point) 11.32 VSTR (floating-point) 11.33 VSTR (post-increment and pre-decrement, floating-point) 11.34 VSUB (floating-point) 12 Directives Reference 12.1 Alphabetical list of directives 12.2 About assembly control directives 12.3 About frame directives 12.4 ALIAS 12.5 ALIGN 12.6 AREA 12.7 ARM or CODE32 12.8 ASSERT 12.9 ATTR 12.10 CN 12.11 CODE16 12.12 COMMON 12.13 CP 12.14 DATA 12.15 DCB 12.16 DCD and DCDU 12.17 DCDO 12.18 DCFD and DCFDU 12.19 DCFS and DCFSU 12.20 DCI 12.21 DCQ and DCQU 12.22 DCW and DCWU 12.23 DN and SN 12.24 END 12.25 ENDFUNC or ENDP 12.26 ENTRY 12.27 EQU 12.28 EXPORT or GLOBAL 12.29 EXPORTAS 12.30 FIELD 12.31 FRAME ADDRESS 12.32 FRAME POP 12.33 FRAME PUSH 12.34 FRAME REGISTER 12.35 FRAME RESTORE 12.36 FRAME RETURN ADDRESS 12.37 FRAME SAVE 12.38 FRAME STATE REMEMBER 12.39 FRAME STATE RESTORE 12.40 FRAME UNWIND ON 12.41 FRAME UNWIND OFF 12.42 FUNCTION or PROC 12.43 GBLA, GBLL, and GBLS 12.44 GET or INCLUDE 12.45 IF, ELSE, ENDIF, and ELIF 12.46 IMPORT and EXTERN 12.47 INCBIN 12.48 INFO 12.49 KEEP 12.50 LCLA, LCLL, and LCLS 12.51 LTORG 12.52 MACRO and MEND 12.53 MAP 12.54 MEXIT 12.55 NOFP 12.56 OPT 12.57 RELOC 12.58 REQUIRE 12.59 REQUIRE8 and PRESERVE8 12.60 RLIST 12.61 RN 12.62 ROUT 12.63 SETA, SETL, and SETS 12.64 SPACE or FILL 12.65 THUMB 12.66 THUMBX 12.67 TTL and SUBT 12.68 WHILE and WEND 13 Via File Syntax 13.1 Overview of via files 13.2 Via file syntax rules List of Figures 2-1 Organization of general-purpose registers and Program Status Registers 8-1 VFP extension register bank 8-2 VFPv2 register banks 8-3 VFPv3 register banks 10-1 ASR #3 10-2 LSR #3 10-3 LSL #3 10-4 ROR #3 10-5 RRX List of Tables 2-1 ARM processor modes 2-2 Predeclared core registers 2-3 Predeclared extension registers 2-4 Predeclared coprocessor registers 2-5 Instruction groups 4-1 ARM state immediate values (8-bit) 4-2 ARM state immediate values in MOV instructions 4-3 32-bit Thumb immediate values 4-4 32-bit Thumb immediate values in MOV instructions 4-5 Stack-oriented suffixes and equivalent addressing mode suffixes 4-6 Suffixes for load and store multiple instructions 4-7 Changes from earlier ARM assembly language 4-8 Relaxation of requirements 4-9 Differences between pre-UAL Thumb syntax and UAL syntax 5-1 Condition code suffixes and related flags 5-2 Condition codes 5-3 Conditional branches only 5-4 All instructions conditional 6-1 Built-in variables 6-2 Built-in Boolean constants 6-3 Predefined macros 6-4 {TARGET_ARCH_ARM} in relation to {TARGET_ARCH_THUMB} 6-5 Command-line options 6-6 armcc equivalent command-line options 7-1 Unary operators that return strings 7-2 Unary operators that return numeric or logical values 7-3 Multiplicative operators 7-4 String manipulation operators 7-5 Shift operators 7-6 Addition, subtraction, and logical operators 7-7 Relational operators 7-8 Boolean operators 7-9 Operator precedence in ARM assembly language 7-10 Operator precedence in C 8-1 VFP data type specifiers 8-2 Pre-UAL VFP mnemonics 8-3 Floating-point values for use with FCONST 9-1 Compatible processor or architecture combinations 9-2 Severity of diagnostic messages 9-3 Specifying a command-line option and an AREA directive for GNU-stack sections 10-1 Summary of ARM and Thumb instructions 10-2 Condition code suffixes 10-3 PC-relative offsets 10-4 Register-relative offsets 10-5 B instruction availability and range 10-6 BL instruction availability and range 10-7 BLX instruction availability and range 10-8 BX instruction availability and range 10-9 BXJ instruction availability and range 10-10 Offsets and architectures, LDR, word, halfword, and byte 10-11 PC-relative offsets 10-12 Options and architectures, LDR (register offsets) 10-13 Register-relative offsets 10-14 Offsets and architectures, LDR (User mode) 10-15 Offsets and architectures, STR, word, halfword, and byte 10-16 Options and architectures, STR (register offsets) 10-17 Offsets and architectures, STR (User mode) 10-18 Range and encoding of expr 11-1 Summary of VFP instructions 12-1 List of directives 12-2 OPT directive settings
好的,我理解了你的问题。以下是一个简单的C程序,利用互斥锁实现两个进程对同一个文件的互斥写入。 ```c #include <stdio.h> #include <stdlib.h> #include <pthread.h> volatile int lock = 1; // 锁变量,初始值为1 void *write_file(void *arg) { int id = *(int *)arg; char filename[20], content[30]; sprintf(filename, "MYFILE%d", id); sprintf(content, "%03dPROC%d %s", id, id, filename); while (1) { while (lock == 0); // 忙等待锁释放 __sync_lock_test_and_set(&lock, 0); // 上锁 FILE *fp = fopen(filename, "a"); if (fp != NULL) { fprintf(fp, "%s\n", content); fclose(fp); } __sync_lock_release(&lock); // 释放锁 } } int main() { pthread_t tid[2]; int ids[2] = {1, 2}; pthread_create(&tid[0], NULL, write_file, &ids[0]); pthread_create(&tid[1], NULL, write_file, &ids[1]); pthread_join(tid[0], NULL); pthread_join(tid[1], NULL); return 0; } ``` 解释一下代码: 1. 定义了一个 `volatile int` 类型的变量 `lock`,用于表示锁的状态,初始值为1,表示锁被释放。 2. 定义了一个线程函数 `write_file`,该函数接受一个指针参数 `arg`,其中存储了进程的ID。 3. 在 `write_file` 函数中,使用 `sprintf` 函数生成文件名和写入内容。 4. 使用一个死循环,不断地进行文件写入操作。在每次循环开始时,先进行忙等待锁的操作,直到锁被释放为止,然后使用 `__sync_lock_test_and_set` 函数上锁,进行文件写入操作,最后使用 `__sync_lock_release` 函数释放锁。 5. 在 `main` 函数中,创建两个线程,并传入线程函数 `write_file` 和参数 `ids`。 6. 使用 `pthread_join` 函数等待线程执行完成。 关于锁的实现,这里使用了 `__sync_lock_test_and_set` 和 `__sync_lock_release` 函数,这两个函数可以实现原子操作,保证了在多线程环境下的锁的正确性。在 x86 平台上,这两个函数对应的汇编语句是 `xchg` 和 `cmp`;在 ARM 平台上,对应的汇编语句是 `ldrex`、`strex` 和 `cmp`。

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