dsp 28377在线升级 实例总结

原创 2017年01月03日 14:57:22

使用dsp品台28377d来实现在线升级的功能。


方案 : 升级程序  +  应用程序


升级程序 : 主要的目的是将上位机发送过来的应用程序数据(ccs编译生成的.bin文件)烧写到指定位置,之后在跳转到应用程序执行。


应用程序 : 等待升级的程序



//-------------------------------------------------------------------------------------------------------------------------------------------------------------------

升级代码段 :


flash_programming_cpu01.c
1 //#########################################################################
2 // FILE: flash_programming_cpu01.c
3 // TITLE: Flash Programming Example for F2837xD.
4 //
5 //! \addtogroup dual_example_list
6 //! <h1> Flash Programming </h1>
7 //!
8 //! This example demonstrates F021 Flash API usage.
9 //
10 //#########################################################################
11 // $TI Release: F2837xD Support Library v170 $
12 // $Release Date: Mon Sep 21 16:52:10 CDT 2015 $
13 // $Copyright: Copyright (C) 2013-2015 Texas Instruments Incorporated -
14 // http://www.ti.com/ ALL RIGHTS RESERVED $
15 //#########################################################################
16
17 #include "F28x_Project.h" // Device Headerfile and Examples Include	File
18 #include "F2837xD_Ipc_drivers.h"
19
20 #include <string.h>
21
22 //Include Flash API example header file
23 #include "flash_programming_c28.h"
24
25 #define ENTRYADDR 0x88000
26
27 extern void lightflash(void);
28
29 //*************************************************************************
30 // FILE Flash API include file
31 //*************************************************************************
32 #include "F021_F2837xD_C28x.h"
33
34 //Data/Program Buffer used for testing the flash API functions
35 #define WORDS_IN_FLASH_BUFFER 3608 // Programming data buffer, words
36
37 uint16 Buffer[WORDS_IN_FLASH_BUFFER + 1];
38 uint32 *Buffer32 = (uint32 *)Buffer;
39
40 #pragma DATA_SECTION(pbuffer , "PDATASAVE");
41 uint16 pbuffer[WORDS_IN_FLASH_BUFFER]= {
42 #include "P_DATA.h"
43 };
44
45 //*************************************************************************
46 // Prototype of the functions used in this example
47 //*************************************************************************
48 void Example_CallFlashAPI(void);
49
50 //*************************************************************************
51 // This is an example code demonstrating F021 Flash API usage.
52 // This code is in Flash
53 //*************************************************************************
54 void main(void)
55 {
56 // Step 1. Initialize System Control:
57 // Enable Peripheral Clocks
58 // This example function is found in the F2837xD_SysCtrl.c file.
59 InitSysCtrl();
60
61 IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);
62
63 InitGpio();
64
65 InitPieCtrl();
66
67 IER = 0x0000;
68 IFR = 0x0000;
69
70 InitPieVectTable();
71
72 EINT; // Enable Global interrupt INTM
73
74 // Jump to RAM and call the Flash API functions
75 Example_CallFlashAPI();
76
77 DELAY_US(100000);
78
79 static void (*APPEntry)(void);
80
81 APPEntry = (void (*)(void))(ENTRYADDR);
82
83 ESTOP0;
84
85 (*APPEntry)();
86
87 while(1);
88
89 }
90
91 //*************************************************************************
92 // Example_CallFlashAPI
93 //
94 // This function will interface to the flash API.
95 // Flash API functions used in this function are executed from RAM
96 //*************************************************************************
97 #pragma CODE_SECTION(Example_CallFlashAPI , "ramfuncs");
98 void Example_CallFlashAPI(void)
99 {
100 uint32 u32Index = 0;
101 uint16 i = 0;
102
103 Fapi_StatusType oReturnCheck;
104 volatile Fapi_FlashStatusType oFlashStatus;
105
106 // Gain pump semaphore
107 SeizeFlashPump();
108
109 EALLOW;
110 Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0x0;
111 EDIS;
112
113 EALLOW;
114
115 oReturnCheck = Fapi_initializeAPI(F021_CPU0_BASE_ADDRESS, 200);//for now keeping it out
116
117 if(oReturnCheck != Fapi_Status_Success)
118 {
119 // Check Flash API documentation for possible errors
120 while(1);
121 }
122
123 oReturnCheck = Fapi_setActiveFlashBank(Fapi_FlashBank0);
124 if(oReturnCheck != Fapi_Status_Success)
125 {
126 // Check Flash API documentation for possible errors
127 while(1);
128 }
129
130 oReturnCheck = Fapi_issueAsyncCommandWithAddress(Fapi_EraseSector,
131 (uint32 *)ENTRYADDR);
132
133 while (Fapi_checkFsmForReady() != Fapi_Status_FsmReady){}
134
135 // In this case just fill a buffer with data to program into the flash.
136 for(i=0, u32Index = ENTRYADDR;
137
138 (u32Index < (ENTRYADDR + WORDS_IN_FLASH_BUFFER))&& (oReturnCheck ==Fapi_Status_Success);
139
140 i=i+1, u32Index = u32Index + 1)
141 {
142 oReturnCheck = Fapi_issueProgrammingCommand((uint32 *)u32Index,&pbuffer[i],
143 1,
144 0,
145 0,
146 Fapi_DataOnly);
147
148 while(Fapi_checkFsmForReady() == Fapi_Status_FsmBusy);
149
150 if(oReturnCheck != Fapi_Status_Success)
151 {
152 // Check Flash API documentation for possible errors
153 while(1);
154 }
155
156 // Read FMSTAT register contents to know the status of FSM after
157 // program command for any debug
158 oFlashStatus = Fapi_getFsmStatus();
159 }
160
161 // Leave control over flash pump
162 ReleaseFlashPump();
163 }


第98行的函数 :

Example_CallFlashAPI(void)

将数据烧写到地址为0x88000地址为首地址的flash内存当中。并且函数在ramfunc中运行,ramfunc和首地址的跳转在cmd文件中有体现


2837xD_FLASH_lnk_cpu1.cmd

MEMORY
3 {
4 PAGE 0 : /* Program Memory */
5 /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for dataallocation */
6 /* BEGIN is used for the "boot to Flash" bootloader mode */
78
BEGIN : origin = 0x080000, length = 0x000002
9 RAMM0 : origin = 0x000122, length = 0x0002DE
10 RAMD0 : origin = 0x00B000, length = 0x000800
11 RAMLS0 : origin = 0x008000, length = 0x000800
12 RAMLS1 : origin = 0x008800, length = 0x000800
13 RAMLS2 : origin = 0x009000, length = 0x000800
14 RAMLS3 : origin = 0x009800, length = 0x000800
15 RAMLS4 : origin = 0x00A000, length = 0x000800
16 RAMGS14 : origin = 0x01A000, length = 0x001000
17 RAMGS15 : origin = 0x01B000, length = 0x001000
18 RESET : origin = 0x3FFFC0, length = 0x000002
19
20 /* Flash sectors */
21 FLASHA : origin = 0x080002, length = 0x001FFE /* on-chipFlash */
22 FLASHB : origin = 0x082000, length = 0x002000 /* on-chipFlash */
23 FLASHC : origin = 0x084000, length = 0x002000 /* on-chipFlash */
24 FLASHD : origin = 0x086000, length = 0x002000 /* on-chipFlash */
25 FLASHE : origin = 0x088000, length = 0x008000 /* on-chipFlash */
26 FLASHF : origin = 0x090000, length = 0x008000 /* on-chipFlash */
27 FLASHG : origin = 0x098000, length = 0x008000 /* on-chipFlash */
28 FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chipFlash */
29 FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chipFlash */
30 FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chipFlash */
31 FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chipFlash */
32 FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chipFlash */
33 FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chipFlash */
34 FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chipFlash */

36 PAGE 1 : /* Data Memory */
37 /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for programallocation */
38
39 BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part ofM0, BOOT rom will use this for stack */
40 RAMM1 : origin = 0x000400, length = 0x000400 /* on-chipRAM block M1 */
41 RAMD1 : origin = 0x00B800, length = 0x000800
42
43 RAMLS5 : origin = 0x00A800, length = 0x000800
44
45 RAMGS0 : origin = 0x00C000, length = 0x001000
46 RAMGS1 : origin = 0x00D000, length = 0x001000
47 RAMGS2 : origin = 0x00E000, length = 0x001000
48 RAMGS3 : origin = 0x00F000, length = 0x001000
49 RAMGS4 : origin = 0x010000, length = 0x001000
50 RAMGS5 : origin = 0x011000, length = 0x001000
51 RAMGS6 : origin = 0x012000, length = 0x001000
52 RAMGS7 : origin = 0x013000, length = 0x001000
53 RAMGS8 : origin = 0x014000, length = 0x001000
54 RAMGS9 : origin = 0x015000, length = 0x001000
55 RAMGS10 : origin = 0x016000, length = 0x001000
56 RAMGS11 : origin = 0x017000, length = 0x001000
57 RAMGS12 : origin = 0x018000, length = 0x001000
58 RAMGS13 : origin = 0x019000, length = 0x001000
59
60
61 CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
62 CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
63 }
64
65
66 SECTIONS
67 {
68 /* Allocate program areas: */
69 .cinit : > FLASHB PAGE = 0, ALIGN(4)
70 .pinit : > FLASHB, PAGE = 0, ALIGN(4)
71 .text : >> FLASHB | FLASHC | FLASHD PAGE = 0,ALIGN(4)
72 codestart : > BEGIN PAGE = 0, ALIGN(4)
73 ramfuncs : LOAD = FLASHD,
74 RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
75 LOAD_START(_RamfuncsLoadStart),
76 LOAD_SIZE(_RamfuncsLoadSize),
77 LOAD_END(_RamfuncsLoadEnd),
78 RUN_START(_RamfuncsRunStart),
79 RUN_SIZE(_RamfuncsRunSize),
80 RUN_END(_RamfuncsRunEnd),
81 PAGE = 0, ALIGN(4)
82
83 /* Allocate uninitalized data sections: */
84 .stack : > RAMM1 PAGE = 1
85 .ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1
86 .esysmem : > RAMLS5 PAGE = 1
87
88 /* Initalized sections go in Flash */
89 .econst : >> FLASHF | FLASHG | FLASHH PAGE = 0,ALIGN(4)
90 .switch : > FLASHB PAGE = 0, ALIGN(4)
91
92 .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used,*/
93
94 Filter_RegsFile : > RAMGS0, PAGE = 1
95
96 SHARERAMGS0 : > RAMGS0, PAGE = 1
97 SHARERAMGS1 : > RAMGS1, PAGE = 1
98 ramgs0 : > RAMGS0, PAGE = 1
99 ramgs1 : > RAMGS1, PAGE = 1
100
101 #ifdef __TI_COMPILER_VERSION
102 #if __TI_COMPILER_VERSION >= 15009000
103 .TI.ramfunc : {} LOAD = FLASHD,
104 RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
105 LOAD_START(_RamfuncsLoadStart),
106 LOAD_SIZE(_RamfuncsLoadSize),
107 LOAD_END(_RamfuncsLoadEnd),
108 RUN_START(_RamfuncsRunStart),
109 RUN_SIZE(_RamfuncsRunSize),
110 RUN_END(_RamfuncsRunEnd),
111 PAGE = 0, ALIGN(4)
112 #endif
113 #endif
114
115 /* The following section definitions are required when using the IPC API Drivers */
116 GROUP : > CPU1TOCPU2RAM, PAGE = 1
117 {
118 PUTBUFFER
119 PUTWRITEIDX
120 GETREADIDX
121 }
122
123 GROUP : > CPU2TOCPU1RAM, PAGE = 1
124 {
125 GETBUFFER : TYPE = DSECT
126 GETWRITEIDX : TYPE = DSECT
127 PUTREADIDX : TYPE = DSECT
128 }
129
130 /* The following section definition are for SDFM examples */
131 Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
132 Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
133 Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
134 Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
135 Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
136 PDATASAVE : > RAMGS0 , PAGE = 1
137
138 }
139
140 /*
141 //=========================================================================
==
142 // End of file.
143 //=========================================================================
==
144 */
145




应用程序代码如下所示 :

blinky_cpu01.c
1 //#########################################################################
2 // FILE: blinky_cpu01.c
3 // TITLE: LED Blink Example for F2837xD.
4 //
5 //! \addtogroup cpu01_example_list
6 //! <h1> Blinky </h1>
7 //!
8 //! This example blinks LED X
9 //
10 //#########################################################################
11 // $TI Release: F2837xD Support Library v180 $
12 // $Release Date: Fri Nov 6 16:19:46 CST 2015 $
13 // $Copyright: Copyright (C) 2013-2015 Texas Instruments Incorporated -
14 // http://www.ti.com/ ALL RIGHTS RESERVED $
15 //#########################################################################
16
17 #include "F28x_Project.h" // Device Headerfile and Examples IncludeFile
18 #include <string.h>
19
20 Uint16 test = 0;
21
22 //void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel);
23 //***************************************************************
24 //usart initial block
25 //***************************************************************
26 void UsartInit(void)
27 {
28 GPIO_SetupPinMux(28, GPIO_MUX_CPU1, 1);
29 GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_PUSHPULL);
30 GPIO_SetupPinMux(29, GPIO_MUX_CPU1, 1);
31 GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
32
33 //---- USART configuration ----------
34 SciaRegs.SCIFFTX.all=0xE040;
35 SciaRegs.SCIFFRX.all=0x2044;
36 SciaRegs.SCIFFCT.all=0x0;
37
38 SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
39 // No parity,8 char bits,
40 // async mode, idle-line protocol
41 SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
42 // Disable RX ERR, SLEEP, TXWAKE
43 SciaRegs.SCICTL2.all =0x0003;
44 SciaRegs.SCICTL2.bit.TXINTENA =1;
45 SciaRegs.SCICTL2.bit.RXBKINTENA =1;
46 SciaRegs.SCIHBAUD.all =0x0002;
Page 1blinky_cpu01.c
47 SciaRegs.SCILBAUD.all =0x008B;
48 // SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back
49 SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
50
51 //-DMA configuration
52 }
53
54 //***************************************************************
55 //usart UsartSendData block
56 //just fit for 8 bit data to send
57 //***************************************************************
58 void UsartSendData(uint16_t data_in)
59 {
60 SciaRegs.SCITXBUF.all = data_in;
61 while(SciaRegs.SCIFFTX.bit.TXFFST !=0); // wait for RRDY/RXFFST =1 fordata available in FIFO
62 }
63
64
65 void main(void)
66 {
67 InitSysCtrl();
68
69 InitGpio();
70
71 DINT;
72
73 InitPieCtrl();
74
75 // Disable CPU interrupts and clear all CPU interrupt flags:
76 IER = 0x0000;
77 IFR = 0x0000;
78
79 InitPieVectTable();
80
81 EINT; // Enable Global interrupt INTM
82
83 UsartInit();
84
85
86 EALLOW;
87 GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0;
88 GpioCtrlRegs.GPADIR.bit.GPIO10 = 1;
89 EDIS;
90
91 GpioDataRegs.GPADAT.bit.GPIO10 = 0;
92
93 while(1){
94
95 GpioDataRegs.GPADAT.bit.GPIO10 = 0;
96
97 DELAY_US(50000);
98
99 GpioDataRegs.GPADAT.bit.GPIO10 = 1;
100
101 DELAY_US(50000);
102
103 if(test == 255) test = 0;
104
105 test = test + 1;
106
107 UsartSendData(test);
108
109 DELAY_US(1000);
110 }
123 }
124

应用程序在调试的时候出现了一个问题 :

就是在在线调试的过程中,从升级程序跳转到应用程序的时候:

static void (*APPEntry)(void);
80
81 APPEntry = (void (*)(void))(ENTRYADDR);
82
83 ESTOP0;
84
85 (*APPEntry)();

进入应用程序,应用程序总是会在一些地方跳转到异常中断,最后找问题找到是在应用程序中的IntiFlash()函数,屏蔽掉该函数就正常啦。


IntiFlash()函数是嵌入到InitSysCtrl();中,就是应用程序最开始调用的那个函数。


2837xD_FLASH_lnk_cpu1.cmd
12
MEMORY
3 {
4 PAGE 0 : /* Program Memory */
5 /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
6 /* BEGIN is used for the "boot to Flash" bootloader mode */
78
BEGIN : origin = 0x088000, length = 0x000002
9 RAMM0 : origin = 0x000122, length = 0x0002DE
10 RAMD0 : origin = 0x00B000, length = 0x000800
11 RAMLS0 : origin = 0x008000, length = 0x000800
12 RAMLS1 : origin = 0x008800, length = 0x000800
13 RAMLS2 : origin = 0x009000, length = 0x000800
14 RAMLS3 : origin = 0x009800, length = 0x000800
15 RAMLS4 : origin = 0x00A000, length = 0x000800
16 RAMGS14 : origin = 0x01A000, length = 0x001000
17 RAMGS15 : origin = 0x01B000, length = 0x001000
18 RESET : origin = 0x3FFFC0, length = 0x000002
19
20 /* Flash sectors */
21 FLASHA : origin = 0x080002, length = 0x001FFE /* on-chipFlash */
22 FLASHB : origin = 0x082000, length = 0x002000 /* on-chipFlash */
23 FLASHC : origin = 0x084000, length = 0x002000 /* on-chipFlash */
24 FLASHD : origin = 0x086000, length = 0x002000 /* on-chipFlash */
25 FLASHE : origin = 0x088002, length = 0x007FFE /* on-chipFlash */
26 FLASHF : origin = 0x090000, length = 0x008000 /* on-chipFlash */
27 FLASHG : origin = 0x098000, length = 0x008000 /* on-chipFlash */
28 FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chipFlash */
29 FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chipFlash */
30 FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chipFlash */
31 FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chipFlash */
32 FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chipFlash */
33 FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chipFlash */
34 FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chipFlash */
35
Page 12837xD_FLASH_lnk_cpu1.cmd
36 PAGE 1 : /* Data Memory */
37 /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for programallocation */
38
39 BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part ofM0, BOOT rom will use this for stack */
40 RAMM1 : origin = 0x000400, length = 0x000400 /* on-chipRAM block M1 */
41 RAMD1 : origin = 0x00B800, length = 0x000800
42
43 RAMLS5 : origin = 0x00A800, length = 0x000800
44
45 RAMGS0 : origin = 0x00C000, length = 0x001000
46 RAMGS1 : origin = 0x00D000, length = 0x001000
47 RAMGS2 : origin = 0x00E000, length = 0x001000
48 RAMGS3 : origin = 0x00F000, length = 0x001000
49 RAMGS4 : origin = 0x010000, length = 0x001000
50 RAMGS5 : origin = 0x011000, length = 0x001000
51 RAMGS6 : origin = 0x012000, length = 0x001000
52 RAMGS7 : origin = 0x013000, length = 0x001000
53 RAMGS8 : origin = 0x014000, length = 0x001000
54 RAMGS9 : origin = 0x015000, length = 0x001000
55 RAMGS10 : origin = 0x016000, length = 0x001000
56 RAMGS11 : origin = 0x017000, length = 0x001000
57 RAMGS12 : origin = 0x018000, length = 0x001000
58 RAMGS13 : origin = 0x019000, length = 0x001000
59
60
61 CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
62 CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
63 }
64
65
66 SECTIONS
67 {
68 /* Allocate program areas: */
69 .cinit : > FLASHE PAGE = 0, ALIGN(4)
70 .pinit : > FLASHE, PAGE = 0, ALIGN(4)
71 .text : >> FLASHE PAGE = 0, ALIGN(4)
72 codestart : > BEGIN PAGE = 0, ALIGN(4)
73 ramfuncs : LOAD = FLASHE,
74 RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
75 LOAD_START(_RamfuncsLoadStart),
76 LOAD_SIZE(_RamfuncsLoadSize),
77 LOAD_END(_RamfuncsLoadEnd),
78 RUN_START(_RamfuncsRunStart),
79 RUN_SIZE(_RamfuncsRunSize),
80 RUN_END(_RamfuncsRunEnd),
81 PAGE = 0, ALIGN(4)
82
83 /* Allocate uninitalized data sections: */
84 .stack : > RAMM1 PAGE = 1
85 .ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1
86 .esysmem : > RAMLS5 PAGE = 1
87
88 /* Initalized sections go in Flash */
89 .econst : >> FLASHE PAGE = 0, ALIGN(4)
90 .switch : > FLASHE PAGE = 0, ALIGN(4)
91
92 .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used,*/
93
94 Filter_RegsFile : > RAMGS0, PAGE = 1
95
96 SHARERAMGS0 : > RAMGS0, PAGE = 1
97 SHARERAMGS1 : > RAMGS1, PAGE = 1
98 ramgs0 : > RAMGS0, PAGE = 1
99 ramgs1 : > RAMGS1, PAGE = 1
100
101 #ifdef __TI_COMPILER_VERSION
102 #if __TI_COMPILER_VERSION >= 15009000
103 .TI.ramfunc : {} LOAD = FLASHE,
104 RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
105 LOAD_START(_RamfuncsLoadStart),
106 LOAD_SIZE(_RamfuncsLoadSize),
107 LOAD_END(_RamfuncsLoadEnd),
108 RUN_START(_RamfuncsRunStart),
109 RUN_SIZE(_RamfuncsRunSize),
110 RUN_END(_RamfuncsRunEnd),
111 PAGE = 0, ALIGN(4)
112 #endif
113 #endif
114
115 /* The following section definitions are required when using the IPC APIDrivers */
116 GROUP : > CPU1TOCPU2RAM, PAGE = 1
117 {
118 PUTBUFFER
119 PUTWRITEIDX
120 GETREADIDX
121 }
122
123 GROUP : > CPU2TOCPU1RAM, PAGE = 1
124 {
125 GETBUFFER : TYPE = DSECT
126 GETWRITEIDX : TYPE = DSECT
127 PUTREADIDX : TYPE = DSECT
128 }
129
130 /* The following section definition are for SDFM examples */
131 Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
132 Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
133 Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
134 Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
135 Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
136
137 }
138
139 /*
140 //=========================================================================
==
141 // End of file.
142 //=========================================================================
==
143 */
144

升级程序完成,可用




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F28377D学习系列(一)

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ucos-ii在ti dsp 28377芯片上的运行过程和移植过程

2017/2/10 ucos­ii在ti dsp 28377 芯片上的运行过程和移植过程 ­ havihouston ­博客园 http://www .cnblogs.com/havihousto...

使用28377S进行ADC采样时配置错误导致波形畸变问题

虽现在想起来这是个很傻的问题,DSP开发经验严重不足导致走了很多弯路,希望看这篇文章的各位都能够避免这个问题哈,如果不小心遇到了跟我同样的问题,也可以稍微节省一点时间。 问题描述:使用DSP 283...

TMS320F28335学习笔记——ADC详解

TMS320F28335内部包含12位AD转换器,其功能有: 具有内置(采样保持)S/H的12位ADC内核 模拟输入:0.0V至3.0V(高于3.0V的电压产生满刻度转换结果)。 快速转换率:在...

DSP程序死机(跑飞)的一些情况-硬件原因

 DSP和FPGA不一样,在DSP上运行的程序可能会会出现死机,也就是跑飞的情况,查死机基本是每个DSP或嵌入式工程师debug时都会经历过的。DSP死机可能是硬件造成的也可能是软件造成。 先...

关于DSP的boot mode / boot loader /上电顺序 /在线升级等问题的总结

使用器件 ti dsp c2000 2837x 1、dsp的上电过程和boot mode以及boot loader   1)dsp的上电顺序, 对于双核系统而言 , 他...
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