FPGA自动配置CDCM6208的实现代码

`define reg_0_data 	 'h01B9
`define reg_1_data 	 'h0030
`define reg_2_data 	 'h0195
`define reg_3_data 	 'h08F5
`define reg_4_data 	 'h20D7
`define reg_5_data 	 'h0023
`define reg_6_data 	 'h003B
`define reg_7_data 	 'h0023
`define reg_8_data 	 'h001D
`define reg_9_data 	 'h0003
`define reg_10_data 	 'h0130
`define reg_11_data 	 'h0000
`define reg_12_data 	 'h0003
`define reg_13_data 	 'h00E0
`define reg_14_data 	 'h0000
`define reg_15_data 	 'h0003
`define reg_16_data 	 'h00E0
`define reg_17_data 	 'h0000
`define reg_18_data 	 'h0003
`define reg_19_data 	 'h00E0
`define reg_20_data 	 'h0000

/*
cfg_rom cfg_rom (  
.clk( clk ) ,
.rst( rst  ) ,
.addr( addr ) ,
.info( info ) ,
.do_rd( do_rd  ) ,
.to_end( to_end  ) 
);
*/ 

module cfg_rom (input clk,rst,
output reg [15:0] addr,
output reg [15:0] info,
input do_rd,
output reg to_end
); 
always@(posedge clk)  if (rst )addr<=0; else if (do_rd) addr<=addr+1;
always @ (*) to_end <= addr == 21;
always @(posedge clk)case (addr[4:0])
0: info <= `reg_0_data ;
1: info <= `reg_1_data ;
2: info <= `reg_2_data ;
3: info <= `reg_3_data ;
4: info <= `reg_4_data ;
5: info <= `reg_5_data ;
6: info <= `reg_6_data ;
7: info <= `reg_7_data ;
8: info <= `reg_8_data ;
9: info <= `reg_9_data ;
10: info <= `reg_10_data ;
11: info <= `reg_11_data ;
12: info <= `reg_12_data ;
13: info <= `reg_13_data ;
14: info <= `reg_14_data ;
15: info <= `reg_15_data ;
16: info <= `reg_16_data ;
17: info <= `reg_17_data ;
18: info <= `reg_18_data ;
19: info <= `reg_19_data ;
20: info <= `reg_20_data ; 
default info <= 0 ; 
endcase 
endmodule 

/*


cdcm6208_cfg  cdcm6208_cfg(
 .clk(   ),
 .rst(   ),
 .start(   ),
 .pin_mosi(   ),
 .pin_sclk(   ),
 .pin_csn(   ),
 .reg pin_rstn(   ),
 .cfg_done (   ) 
);

*/

module  cdcm6208_cfg(
input clk,rst,start,
output pin_mosi,pin_sclk,pin_csn,
output reg pin_rstn,
output reg cfg_done  
);
wire [1:0]cfg_rom_index ;
wire [15:0] addr , info ;
reg   do_rd , cdcm6208_wr ;

cfg_rom cfg_rom (  
.clk( clk ) ,
.rst( rst  ) ,
.addr( addr ) ,
.info( info ) ,
.do_rd( do_rd  ) ,
.to_end( to_end  ) 
);

CDCM6208_spi_master  CDCM6208_spi_master (
.clk( clk),
.rst(rst  ),
.pin_mosi(pin_mosi  ),
.pin_sclk(pin_sclk ),
.pin_csn(pin_csn  ),
.pin_miso( ),
.wr(cdcm6208_wr ),
.busy(cdcm6208_busy ),
.addr(addr ) ,
.din( info  ),
.dout( ) 
);

reg [7:0] st ,d;always @(posedge clk)case (st) 7,30:d<=d+1;default d<=0; endcase
 always @(posedge clk)  if (rst)st <= 0 ;else case (st)
0: st<=5; 
5: if (start) st<=7;
7: if (d==100) st<=10;// set rstn=0 
10:if (cdcm6208_busy==0) st<=15;//  reset info  
15: st <= 17; //do_rd
17 :  st <= 18; //wait data valid 
18 :  st <= 19 ; //cdcm6208_wr =1
19,20,21,22: st<=st+1;
23 : if (cdcm6208_busy==0) st<=24;
24 : if (to_end==0) st<=10 ;else st<= 30 ;
30 : if (d==100)  st<=31;
31 : st <= 33; // set resetn=1;
33 : st<=5;
default st<=0; 
endcase
 
always @(posedge clk) case (st) 7: pin_rstn<=0; 0,31: pin_rstn<=1;endcase 
always @(posedge clk) cdcm6208_wr <= st==18 ; 
always @(posedge clk) do_rd <= st==17 ;
always @(posedge clk) cfg_done <= ( st==5 )&& (start==0) ;  

endmodule 
 

/*
 
CDCM6208_spi_master  CDCM6208_spi_master (
.clk( ),
.rst( ),
.pin_mosi( ),
.pin_sclk( ),
.pin_csn( ),
.pin_miso( ),
.wr( ),
.busy( ),
.addr( ) ,
.din( ),
.dout( ) 
);
 
 */
module CDCM6208_spi_master (
input clk,rst,
output reg  pin_mosi,pin_sclk,pin_csn,
input pin_miso,
input wr,
output busy,
input [15:0] addr ,
input [15:0] din,
output reg [15:0] dout 
);

reg [3:0] d ; always @ (posedge clk) if (rst) d<=0; else d<=d+1;
 
wire move = d == 0; 
 
reg [7:0] st ;
reg [31:0] reg32   ;  always@(posedge clk)  if (wr&st==10) reg32 <= {addr[15:0],din[15:0]};
reg[31:0] result32 ;  always@(posedge clk)  if (st==200  ) dout <= result32[15:0] ;
reg  pin_miso_r    ;  always@(posedge clk)  pin_miso_r<= pin_miso;

always@(posedge clk)   if (st==20) pin_csn <= 1'b0 ; else if ( ( st==202 )  || ( st==0 ) ) pin_csn<= 1'b1 ;
 
 
 
always@(posedge clk)  if (rst) st<=0; else case(st)
0  :  begin  st <= 10 ; pin_mosi<=0;pin_sclk<=0;end  
10 : begin   pin_mosi<=0;pin_sclk<=0; if (  wr  ) st<=20  ;end  
20 :   if ( move ) st<=21  ;
21 :   if ( move ) st<=100 ; 

100: begin   pin_sclk<=0;      pin_mosi<=  reg32[31] ;  if (move) st<=st+1 ;    end 
101: begin   pin_sclk<=1;      pin_mosi<=  reg32[31] ;  result32[31] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
102: begin   pin_sclk<=0;      pin_mosi<=  reg32[30] ;  if (move) st<=st+1 ;    end 
103: begin   pin_sclk<=1;      pin_mosi<=  reg32[30] ;  result32[30] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
104: begin   pin_sclk<=0;      pin_mosi<=  reg32[29] ;  if (move) st<=st+1 ;    end 
105: begin   pin_sclk<=1;      pin_mosi<=  reg32[29] ;  result32[29] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
106: begin   pin_sclk<=0;      pin_mosi<=  reg32[28] ;  if (move) st<=st+1 ;    end 
107: begin   pin_sclk<=1;      pin_mosi<=  reg32[28] ;  result32[28] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
108: begin   pin_sclk<=0;      pin_mosi<=  reg32[27] ;  if (move) st<=st+1 ;    end 
109: begin   pin_sclk<=1;      pin_mosi<=  reg32[27] ;  result32[27] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
110: begin   pin_sclk<=0;      pin_mosi<=  reg32[26] ;  if (move) st<=st+1 ;    end 
111: begin   pin_sclk<=1;      pin_mosi<=  reg32[26] ;  result32[26] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
112: begin   pin_sclk<=0;      pin_mosi<=  reg32[25] ;  if (move) st<=st+1 ;    end 
113: begin   pin_sclk<=1;      pin_mosi<=  reg32[25] ;  result32[25] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
114: begin   pin_sclk<=0;      pin_mosi<=  reg32[24] ;  if (move) st<=st+1 ;    end 
115: begin   pin_sclk<=1;      pin_mosi<=  reg32[24] ;  result32[24] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
116: begin   pin_sclk<=0;      pin_mosi<=  reg32[23] ;  if (move) st<=st+1 ;    end 
117: begin   pin_sclk<=1;      pin_mosi<=  reg32[23] ;  result32[23] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
118: begin   pin_sclk<=0;      pin_mosi<=  reg32[22] ;  if (move) st<=st+1 ;    end 
119: begin   pin_sclk<=1;      pin_mosi<=  reg32[22] ;  result32[22] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
120: begin   pin_sclk<=0;      pin_mosi<=  reg32[21] ;  if (move) st<=st+1 ;    end 
121: begin   pin_sclk<=1;      pin_mosi<=  reg32[21] ;  result32[21] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
122: begin   pin_sclk<=0;      pin_mosi<=  reg32[20] ;  if (move) st<=st+1 ;    end 
123: begin   pin_sclk<=1;      pin_mosi<=  reg32[20] ;  result32[20] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
124: begin   pin_sclk<=0;      pin_mosi<=  reg32[19] ;  if (move) st<=st+1 ;    end 
125: begin   pin_sclk<=1;      pin_mosi<=  reg32[19] ;  result32[19] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
126: begin   pin_sclk<=0;      pin_mosi<=  reg32[18] ;  if (move) st<=st+1 ;    end 
127: begin   pin_sclk<=1;      pin_mosi<=  reg32[18] ;  result32[18] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
128: begin   pin_sclk<=0;      pin_mosi<=  reg32[17] ;  if (move) st<=st+1 ;    end 
129: begin   pin_sclk<=1;      pin_mosi<=  reg32[17] ;  result32[17] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
130: begin   pin_sclk<=0;      pin_mosi<=  reg32[16] ;  if (move) st<=st+1 ;    end 
131: begin   pin_sclk<=1;      pin_mosi<=  reg32[16] ;  result32[16] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
132: begin   pin_sclk<=0;      pin_mosi<=  reg32[15] ;  if (move) st<=st+1 ;    end 
133: begin   pin_sclk<=1;      pin_mosi<=  reg32[15] ;  result32[15] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
134: begin   pin_sclk<=0;      pin_mosi<=  reg32[14] ;  if (move) st<=st+1 ;    end 
135: begin   pin_sclk<=1;      pin_mosi<=  reg32[14] ;  result32[14] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
136: begin   pin_sclk<=0;      pin_mosi<=  reg32[13] ;  if (move) st<=st+1 ;    end 
137: begin   pin_sclk<=1;      pin_mosi<=  reg32[13] ;  result32[13] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
138: begin   pin_sclk<=0;      pin_mosi<=  reg32[12] ;  if (move) st<=st+1 ;    end 
139: begin   pin_sclk<=1;      pin_mosi<=  reg32[12] ;  result32[12] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
140: begin   pin_sclk<=0;      pin_mosi<=  reg32[11] ;  if (move) st<=st+1 ;    end 
141: begin   pin_sclk<=1;      pin_mosi<=  reg32[11] ;  result32[11] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
142: begin   pin_sclk<=0;      pin_mosi<=  reg32[10] ;  if (move) st<=st+1 ;    end 
143: begin   pin_sclk<=1;      pin_mosi<=  reg32[10] ;  result32[10] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
144: begin   pin_sclk<=0;      pin_mosi<=  reg32[9] ;  if (move) st<=st+1 ;    end 
145: begin   pin_sclk<=1;      pin_mosi<=  reg32[9] ;  result32[9] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
146: begin   pin_sclk<=0;      pin_mosi<=  reg32[8] ;  if (move) st<=st+1 ;    end 
147: begin   pin_sclk<=1;      pin_mosi<=  reg32[8] ;  result32[8] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
148: begin   pin_sclk<=0;      pin_mosi<=  reg32[7] ;  if (move) st<=st+1 ;    end 
149: begin   pin_sclk<=1;      pin_mosi<=  reg32[7] ;  result32[7] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
150: begin   pin_sclk<=0;      pin_mosi<=  reg32[6] ;  if (move) st<=st+1 ;    end 
151: begin   pin_sclk<=1;      pin_mosi<=  reg32[6] ;  result32[6] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
152: begin   pin_sclk<=0;      pin_mosi<=  reg32[5] ;  if (move) st<=st+1 ;    end 
153: begin   pin_sclk<=1;      pin_mosi<=  reg32[5] ;  result32[5] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
154: begin   pin_sclk<=0;      pin_mosi<=  reg32[4] ;  if (move) st<=st+1 ;    end 
155: begin   pin_sclk<=1;      pin_mosi<=  reg32[4] ;  result32[4] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
156: begin   pin_sclk<=0;      pin_mosi<=  reg32[3] ;  if (move) st<=st+1 ;    end 
157: begin   pin_sclk<=1;      pin_mosi<=  reg32[3] ;  result32[3] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
158: begin   pin_sclk<=0;      pin_mosi<=  reg32[2] ;  if (move) st<=st+1 ;    end 
159: begin   pin_sclk<=1;      pin_mosi<=  reg32[2] ;  result32[2] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
160: begin   pin_sclk<=0;      pin_mosi<=  reg32[1] ;  if (move) st<=st+1 ;    end 
161: begin   pin_sclk<=1;      pin_mosi<=  reg32[1] ;  result32[1] <= pin_miso_r;if (move) st<=st+1 ;    end 
 
162: begin   pin_sclk<=0;      pin_mosi<=  reg32[0] ;  if (move) st<=st+1 ;    end 
163: begin   pin_sclk<=1;      pin_mosi<=  reg32[0] ;  result32[0] <= pin_miso_r;if (move) st<=200 ;    end 
 
200: begin   pin_sclk<=0; if (move)  st<=st+1;end 
201: begin   pin_sclk<=0; if (move)  st<=st+1;end 
202: begin   pin_sclk<=0; if (move)  st<=st+1;end 
203: begin                if (move)  st<=10; end
default st<=0;
endcase
 
assign busy = (wr==1) || (st!=10) ;
 
endmodule 











module tb ;

reg clk,rst,start;
initial {clk,rst,start} = 0 ;


always #5 clk = ~clk ;
initial begin 

$dumpfile ("ttt.vcd");

$dumpvars(0,tb);

#100;

@(posedge clk) ;
rst = 1;
@(posedge clk) ;
@(posedge clk) ;
rst = 0;
@(posedge clk) ;
@(posedge clk) ;
start=1;
@(posedge clk) ;
@(posedge clk) ;
start=0;
#1000000 ;
$finish ;

end 


  cdcm6208_cfg  cdcm6208_cfg(
 .clk( clk ),
 .rst( rst ),
 .start( start  ),
 .pin_mosi(pin_mosi ),
 .pin_sclk(pin_sclk ),
 .pin_csn(pin_csn ),
 .pin_rstn(pin_rstn ),
 .cfg_done(cfg_done )  
);


endmodule