VIVADO 2014.4 如何编写mealy状态机并测试

VIVADO 2014.4 如何编写mealy状态机并测试

1. 题干描述:

Design a sequence detector implementing a Mealy state machine using
three always blocks. The Mealy state machine has one input (ain) and
one output (yout). The output yout is 1 if and only if the total
number of 1s received is divisible by 3 (hint: 0 is inclusive,
however, reset cycle(s) do not count as 0- see in simulation waveform
time=200). Develop a testbench and verify the model through a
behavioral simulation.
即需要实现mealy状态机，该状态机有一个输入（0/1）和一个输出（0/1）。只有累计输入1的个数为3的倍数才会输出1（0个1也输出1）。

2. 理想的仿真波形图：

3.绘制mealy状态机

4.新建项目
请务必保持硬件配置（芯片选项：xc7a35tcpg236-1）正确，其他的选项按新建项目的默认选项来即可
最后一步的图：

5.新建约束文件
新建文件的地方（项目窗口的左侧）：

在弹出来的窗口里选择：

然后在弹出来的地方选择新建一个约束文件：

自己取名字就行，然后把代码拷贝进去：

## Switches
set_property PACKAGE_PIN V17 [get_ports {
   ain}]					
	set_property IOSTANDARD LVCMOS33 [get_ports {
   ain}]
	set_property PACKAGE_PIN R2 [get_ports {
   clk}]					
	set_property IOSTANDARD LVCMOS33 [get_ports {
   clk}]
 

## LEDs
set_property PACKAGE_PIN U16