HDLBits 刷题 Gates and vectors——verilog

Circuits 电路部分 --Gates and vectors

题目内容

You are given a four-bit input vector in [3:0]. We want to know some relationships between each bit and its neighbour:

• out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left (higher index) are '1'. For example, out_both[2] should indicate if in[2] and in[3] are both 1. Since in[3] has no neighbour to the left, the answer is obvious so we don’t need to know out_both[3].

• out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don’t need to know out_any[0].

• out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[2] should indicate if in[2] is different from in[3]. For this part, treat the vector as wrapping around, so in[3]'s neighbour to the left is in[0].

模块声明

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );

题目大意

有四输入向量 in[3:0]，实现输出out_both[2:0]、out_any[3:1]、out_different[3:0]。
功能如下：

-out_both: 此输出向量的每个位都应指示相应的输入位及其左侧的邻居是否为“1”。例如，out_both[2] 应该指示 in[2] 和 in[3] 是否都是 1。

-out_any:此输出向量的每个位都应指示任何相应的输入位及其右侧的邻居是否为“1”。例如，out_any[2] 应该指示in[2]或in[1]是否为1。

-out_different:此输出向量的每个位都应指示相应的输入位是否与其左侧的邻居不同。例如，out_different[2] 应该指示 in[2] 是否与 in[3] 不同。对于这一部分，将向量视为循环向量，因此in[3]左侧的邻居为in[0]。

My Solution

本解法相对复杂了，其实可以通过assign语句来实现。
提示：The both, any, and different outputs use two-input AND, OR, and XOR operations, respectively. Using vectors, this can be done in 3 assign statements.

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
        //Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left (higher index) are '1'. 
    always @ (*)
        begin
            for (integer i = 0; i < 3; i = i + 1)
                out_both[i] = in[i+1] & in[i];
        end
        //Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'. 
    always @(*)
        begin
            for (integer i = 3; i > 0; i = i - 1)
                out_any[i] = in[i] | in[i-1];
        end
        //Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left.
    always @(*)
        begin
            for (integer i = 0; i <= 3; i = i + 1)
                begin
                    if (i < 3)
                        out_different[i] = in[i] ^ in[i+1];
                    else
                        out_different[i] = in[i] ^ in[i-3];
                end
        end
endmodule

仿真时序图

官方Solution

采用 assign 和 位拼接符{} 语句来实现。

module top_module (
	input [3:0] in,
	output [2:0] out_both,
	output [3:1] out_any,
	output [3:0] out_different
);

	// Use bitwise operators and part-select to do the entire calculation in one line of code
	// in[3:1] is this vector:   					 in[3]  in[2]  in[1]
	// in[2:0] is this vector:   					 in[2]  in[1]  in[0]
	// Bitwise-OR produces a 3 bit vector.			   |      |      |
	// Assign this 3-bit result to out_any[3:1]:	o_a[3] o_a[2] o_a[1]

	// Thus, each output bit is the OR of the input bit and its neighbour to the right:
	// e.g., out_any[1] = in[1] | in[0];	
	// Notice how this works even for long vectors.
	assign out_any = in[3:1] | in[2:0];

	assign out_both = in[2:0] & in[3:1];
	
	// XOR 'in' with a vector that is 'in' rotated to the right by 1 position: {in[0], in[3:1]}
	// The rotation is accomplished by using part selects[] and the concatenation operator{}.
	assign out_different = in ^ {in[0], in[3:1]};
	
endmodule