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RSS订阅原创 HDLBits-Lemmings4
题目：状态机：代码：module top_module( input clk, input areset, // Freshly brainwashed Lemmings walk left. input bump_left, input bump_right, input ground, input dig, output walk_left, output walk_right, output aaa..
2021-08-21 20:30:34
321
原创 HDLBits-Lemmings2
题目：状态机：注意：如果像左图那样设计状态机的话，到了S2之后，需要回到S0或者S1，但是这样就没有进行判断的依据了，所以直接设计成右图所示的状态机比较方便。
2021-08-19 17:31:39
241
原创 HDLBits-Design a Moore FSM
题目：题意：一个水库，三个探头S1，S2，S3，两个水流控制器，一个FR3到FR1，一个DFR，水位被这三个探头分成了四个档，第一个水流控制器何时开关如表所示，第二个水流控制器的开关由前后水位的比较来决定，只有水位变低了才会打开。状态转移图：代码：module top_module ( input clk, input reset, input [3:1] s, output fr3, output fr2, output fr1
2021-08-19 17:25:41
610
原创 HDLBits-Shift register
题目：Implement the following circuit:正确代码：module top_module ( input clk, input resetn, // synchronous reset input in, output reg out); reg [2:0] q; always @ (posedge clk) begin if(!resetn) begin
2021-07-18 17:36:35
217
原创 HDLBits-12-hour clock
题目：Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-runningclk, with a pulse onenawhenever your clock should increment (i.e., once per second).resetresets the clock to 12:00 AM...
2021-07-12 22:40:11
782
原创 HDLBits-Counter 1000
题目：From a 1000 Hz clock, derive a 1 Hz signal, calledOneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, theOneHertzsignal mu...
2021-07-10 23:26:02
1157
原创 HDLBits-Dual-edge triggered flip-flop
题目：You're familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge triggered flip-flops, and
2021-07-10 21:08:33
1105
原创 HDLBits-Edge capture register
题目：For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).Each output bit behaves like a SR flip-flop
2021-07-10 16:14:09
782
原创 HDLBits-K-map implemented with a multiplexer
For the following Karnaugh map, give the circuit implementation using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must useaandbas the multiple...
2021-07-08 22:54:36
813
1
原创 HDLBits-Minimum SOP and POS
A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this syst
2021-07-08 21:54:19
1945
原创 HDLBits-Signed addition overflow
Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.my stupid solution:通过最高位和次高位的进位来判断是否溢出：最高位的进位与次高位的进位异或。another solution:直接.
2021-07-08 17:33:16
1396
原创 HDLBits-256-to-1 multiplexer & 256-to-1 4-bit multiplexer
Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should selectin[0], sel=1 selects bitsin[1], sel=2 selects bitsin[2], etc.
2021-07-08 11:13:49
1691
原创 HDLBits-9-to-1 multiplexer
Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.module top_module( input [15:0] a, b, c, d, e, f, g, h, i, input [3:0] sel, output [15:0] out );
2021-07-08 09:33:07
361
原创 HDLBits-Gates and vectors
You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour:out_both: Each bit of this output vector should indicate whetherboththe corresponding input bit and its neighbour to theleft(higher i...
2021-07-08 09:29:41
253
原创 HDLBits-3-bit population count
A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 3-bit input vector.
2021-07-07 23:10:24
1150
原创 HDLBits-Generate for-loop: 100-bit binary adder 2
Create a 100-bit binary ripple-carry adder by instantiating 100full adders. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out.I.module top_module( input [99:0] a, b, input cin, output [99:0] cout,..
2021-07-07 20:56:18
1441
2
原创 HDLBits-Reduction operators
You're already familiar with bitwise operations between two values, e.g.,a & bora ^ b. Sometimes, you want to create a wide gate that operates on all of the bits ofonevector, like(a[0] & a[1] & a[2] & a[3] ... ), which gets tedious if...
2021-07-07 16:52:17
320
原创 HDLBits-Avoiding latches
To avoid creating latches, all outputs must be assigned a value in all possible conditions (See alsoalways_if2). Simply having adefaultcase is not enough. You must assign a value to all four outputs in all four cases and the default case. This can inv...
2021-07-07 16:26:03
228
原创 HDLBits-Priority encoder with casez
casez treats bits that have the value z as don't care in the comparison.module top_module ( input [7:0] in, output reg [2:0] pos ); always @ (*) begin casez(in) 8'bzzzzzzz1:pos = 3'd0; 8'bzzzzzz1z:pos =
2021-07-07 16:00:39
1068
原创 HDLBits-Adder subtractor
a circuit that can do two operations: (a + b + 0) and (a + ~b + 1).module top_module( input [31:0] a, input [31:0] b, input sub, output [31:0] sum); wire cout; wire [31:0] w1; assign w1 = b ^ {32{sub}}; .
2021-07-07 14:44:42
289
原创 HDLBits-Modules and vectors
module top_module ( input clk, input [7:0] d, input [1:0] sel, output reg [7:0] q ); wire [7:0] q0,q1,q2; //Error: wire q0,q1,q2; my_dff8 my_dff8_0(clk,d,q0); my_dff8 my_dff8_1(clk,q0,q1); my_...
2021-07-07 11:47:18
141
原创 HDLBits-More replication
module top_module( input a,b,c,d,e, output [24:0] out ); assign out = ~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}} ^ {5{a,b,c,d,e}}; //Error: assign out = ~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}} ^ {5{abcde}};endmodule
2021-07-07 11:08:40
134
原创 HDLBits-Replication operator
{num{vector}}Build a circuit thatsign-extends an 8-bit numberto 32 bits. This requires a concatenation of 24 copies of the sign bit(i.e., replicate bit[7] 24 times) followed by the 8-bit number itself.module top_module( input [7:0] in, outp...
2021-07-07 10:53:31
520
原创 HDLBits-Vector reversal 1
Given an 8-bit input vector [7:0], reverse its bits ordering.module top_module( input [7:0] in, output [7:0] out ); assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};endmodulefor-loops:integer i;always @ (*)
2021-07-07 10:35:24
1301
原创 HDLBits-Four wires
module top_module( input a, input b, input c, output w, output x, output y, output z ); assign w = a; assign x = b; assign y = b; assign z = c; //If we're certain about the width of each signal, usin...
2021-07-06 22:45:22
99
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