使用FPGA实现带7段数码显示的模100计数器

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最新推荐文章于 2024-07-19 14:12:25 发布

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分类专栏： FPGA学习文章标签： fpga开发

本文链接：https://blog.csdn.net/CL1983088202/article/details/137869832

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介绍

模100计数器就是一个100进制的计数器。这个设计在实现计数器的基础上将2进制编码的10进制数在7段数码管上进行显示。

数码管展示

转换电路与SSD（七段数码显示）的连接关系是abcdefg，即最高位传递给a，最低位传递给g。

我们可以得到1-10这十个数字与SSD显示的对应关系。

设计文件

模10计数器

library ieee;
use ieee.std_logic_1164.all;
entity counter is
   port(clk: in std_logic;
       digit: out integer range 0 to 9);
end counter;
architecture counter of counter is
begin
   count: process (clk)
       variable temp: integer range 0 to 10;
   begin
       if(clk'event and clk = '1')then
           temp :=temp+1;
           if (temp=10) then temp:=0;
               end if;
       end if;
       digit <= temp;
   end process count;
end counter;

模100计数器

library ieee;
use ieee.std_logic_1164.all;
entity counter is
   port(
           clk,rst : in std_logic;
           digit1,digit2 : out std_logic_vector(6 downto 0));
end counter;
architecture counter of counter is
   begin
   process(rst,clk)
       variable temp1 : integer range 0 to 10;
       variable temp2 : integer range 0 to 10;
   begin
       if(rst = '1') then
           temp1 := 0;
           temp2 := 0;
       elsif(clk'event and clk = '1')then
           temp1 :=temp1 + 1;
           if(temp1 = 10)then
               temp1 := 0;
               temp2 := temp2 + 1;
                   if(temp2 = 10)then
                       temp2 := 0;
                   end if;
           end if;
       end if;
       case temp1 is
           when 0 => digit1 <= "1111110";
           when 1 => digit1 <= "0110000";
           when 2 => digit1 <= "1101101";
           when 3 => digit1 <= "1111001";
           when 4 => digit1 <= "0110011";
           when 5 => digit1 <= "1011011";
           when 6 => digit1 <= "1011111";
           when 7 => digit1 <= "1110000";
           when 8 => digit1 <= "1111111";
           when 9 => digit1 <= "1110011";
           when others => null;
       end case;
       case temp2 is
           when 0 => digit2 <= "1111110";
           when 1 => digit2 <= "0110000";
           when 2 => digit2 <= "1101101";
           when 3 => digit2 <= "1111001";
           when 4 => digit2 <= "0110011";
           when 5 => digit2 <= "1011011";
           when 6 => digit2 <= "1011111";
           when 7 => digit2 <= "1110000";
           when 8 => digit2 <= "1111111";
           when 9 => digit2 <= "1110011";
           when others => null;
       end case;
   end process;
end counter;

测试文件

模10计数器

library ieee;
use ieee.std_logic_1164.all;
entity tb_counter is
end tb_counter;
architecture counter of tb_counter is
component counter
   port(clk: in std_logic;
       digit: out integer range 0 to 9);
end component;
constant clk_period : time :=20ns;
signal clk : std_logic := '0';
signal digit : integer range 0 to 9;
begin
   dut : counter
   port map(
       clk =>clk,
       digit =>digit);
clk_gen:process
begin
   wait for clk_period/2;
   clk <='1';
   wait for clk_period/2;
   clk <='0';
end process;

end;

模100计数器

library ieee;
use ieee.std_logic_1164.all;
entity tb_counter is

end tb_counter;
architecture counter of tb_counter is
   component counter is
       port(
           clk,rst : in std_logic;
           digit1,digit2 : out std_logic_vector(6 downto 0));
   end component counter;
   signal clk,rst : std_logic;
   signal digit1,digit2 : std_logic_vector(6 downto 0);
   begin
       dut : counter
           port map(
                       clk => clk,
                       rst => rst,
                       digit1 => digit1,
                       digit2 => digit2);
       rst <= '0';
       gen_clk : process
           begin
               clk <= '0';
               wait for 10ns;
               clk <= '1';
               wait for 10ns;
       end process;
end counter;