使用FPGA实现一个38译码器_pgam三八译码器-CSDN博客

本文链接：https://blog.csdn.net/CL1983088202/article/details/137689779

最近一直在学习FPGA嘛，在此记录一下整个学习过程吧，希望我能坚持下去，加油啊，张凡。

介绍

首先，简单介绍一下38译码器。译码是编码的逆过程。具有译码功能的逻辑电路称为译码器。假设有m位的输入，那最多可以有2^m的输出。38译码器就是说，输入3位数据，输出8位数据，实现译码的过程。

最近正好在上一门FPGA相关的课程，所以说可能都用VHDL来编程了。我是用的软件和版本分别是quartus13.1和modelsim 10.1。

有什么问题的话，欢迎指正，哈哈哈哈。

38译码器的真值表

直接放图

从上面的真值表中也可以看出，电路有两个输入端口，一个输出端口。其中，输入和输出的对应关系从真值表可以很明显的看出来了。不多废话了。

设计文件

library ieee;
use ieee.std_logic_1164.all;
--38译码器
entity decoder is
port (ena : in std_logic;
       sel : in std_logic_vector(2 downto 0);
       output : out std_logic_vector(7 downto 0));

end decoder;
architecture decoder of decoder is
begin
   process (ena , sel)
       variable temp1 : std_logic_vector (output'high downto 0);
       variable temp2 : integer range 0 to output'high;
       begin
           temp1 := (others =>'1');
           temp2 := 0;
           if(ena = '1')then
               for i in sel'range loop
                   if(sel(i)='1')then
                       temp2 := 2*temp2+1;
                   else
                       temp2 := 2*temp2;
                   end if;
               end loop;
               temp1(temp2) := '0';
           end if;
           output <= temp1;
       end process;
end decoder;

测试文件

library ieee;
use ieee.std_logic_1164.all;
entity tb_decoder is

end tb_decoder;
architecture decoder of tb_decoder is
component decoder is
   port(
           ena : in std_logic;
           sel : in std_logic_vector(2 downto 0);
           output : out std_logic_vector(7 downto 0));
end component decoder;

signal ena : std_logic;
signal sel : std_logic_vector(2 downto 0);
signal output : std_logic_vector(7 downto 0);

begin
   dut : decoder
   port map(
               ena => ena,
               sel => sel,
               output => output);
   process
       begin
           ena <= '0';
           sel <= "000";
           wait for 10ns;
           sel <= "001";
           wait for 10ns;
           sel <= "010";
           wait for 10ns;
           sel <= "011";
           wait for 10ns;
           sel <= "100";
           wait for 10ns;
           sel <= "101";
           wait for 10ns;
           sel <= "110";
           wait for 10ns;
           sel <= "111";
           wait for 10ns;
           ena <= '1';
           sel <= "000";
           wait for 10ns;
           sel <= "001";
           wait for 10ns;
           sel <= "010";
           wait for 10ns;
           sel <= "011";
           wait for 10ns;
           sel <= "100";
           wait for 10ns;
           sel <= "101";
           wait for 10ns;
           sel <= "110";
           wait for 10ns;
           sel <= "111";
           wait;
       end process;