目录
矢量门
module top_module(
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_logical=a||b;
assign out_or_bitwise=a|b;
assign out_not={~b,~a};
endmodule
盖茨4
module top_module(
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and=in[0]&in[1]&in[2]&in[3];
assign out_or=in[0]|in[1]|in[2]|in[3];
assign out_xor=in[0]^in[1]^in[2]^in[3];
endmodule矢量3
下一个矢量
零件选择用于选择向量的部分。级联算子{a，b，c}通过将向量的较小部分连接在一起来创建更大的向量。
{3'b111, 3'b000} => 6'b111000
{1'b1, 1'b0, 3'b101} => 5'b10101
{4'ha, 4'd10} => 8'b10101010 // 4'ha and 4'd10 are both 4'b1010 in binary
级联需要知道每个组件的宽度(或者如何知道结果的长度)。因此，{1, 2, 3}是否为非法，并导致错误消息：在连接中不允许不大小的常量。.
连接运算符既可以用于赋值的左侧，也可以用于赋值的右侧。
input [15:0] in;
output [23:0] out;
assign {out[7:0], out[15:8]} = in; // Swap two bytes. Right side and left side are both 16-bit vectors.
assign out[15:0] = {in[7:0], in[15:8]}; // This is the same thing.
assign out = {in[7:0], in[15:8]}; // This is different. The 16-bit vector on the right is extended to
// match the 24-bit vector on the left, so out[23:16] are zero.
// In the first two examples, out[23:16] are not assigned.
module top_module (
input [4:0] a, b, c, d, e, f,
output [7:0] w, x, y, z );//
assign {w,x,y,z}={a,b,c,d,e,f,2'b11};
// assign { ... } = { ... };
endmodule
矢量反转
module top_module(
input [7:0] in,
output [7:0] out
);
assign out={in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
endmodule
矢量4
module top_module (
input [7:0] in,
output [31:0] out );//
assign out={{24{in[7]}},in};
// assign out = { replicate-sign-bit , the-input };
endmodule矢量5
module top_module (
input a, b, c, d, e,
output [24:0] out );//
assign out=~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}}^{5{a,b,c,d,e}};
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
endmodule模块
注意：.in1后一定要加个空格，否则编译不通过
module top_module ( input a, input b, output out );
// mod_a instance(wa,wb,wc);
mod_a instance1 (.in1 (a), .in2 (b), .out (out));
endmodule模块pos
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a instance1(out1,out2,a,b,c,d); //按照题目的顺序，注意“位置”-->上一题的位置结构
endmodule
模块名
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a instance1( .out1 (out1), .out2 (out2), .in1 (a), .in2 (b), .in3 (c), .in4 (d));
endmodule模块移位
module top_module ( input clk, input d, output q );
wire Q1,Q2;
my_dff instance1(.clk (clk),.d (d),.q (Q1));
my_dff instance2(.clk (clk),.d (Q1),.q (Q2));
my_dff instance3(.clk (clk),.d (Q2),.q (q));
endmodule
模块移位8
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output [7:0] q
);
wire [7:0] q1;
wire [7:0] q2;
wire [7:0] q3;
my_dff8 instance1(.clk (clk),.d (d),.q (q1));
my_dff8 instance2(.clk (clk),.d (q1),.q (q2));
my_dff8 instance3(.clk (clk),.d (q2),.q (q3));
always @(*)begin
case(sel)
2'b00:begin
q = d;
end
2'b01:begin
q = q1;
end
2'b10:begin
q = q2;
end
2'b11:begin
q = q3;
end
endcase
end
endmodule
模块添加
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire cout;
wire [15:0] sum1;
wire [31:16] sum2;
add16 u1_add16(.a (a[15:0]),.b (b[15:0]),.cin (1'b0),.sum (sum1),.cout (cout));
add16 u2_add16(.a (a[31:16]),.b (b[31:16]),.cin (cout),.sum (sum2),.cout ());
assign sum={sum2,sum1};
endmodule模块cseladd
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire[15:0] sum_1;
wire[15:0] sum_2;
wire[15:0] sum_3;
wire cout;
add16 u1_add16(.a (a[15:0]),.b (b[15:0]),.cin (1'b0),.sum (sum_1),.cout (cout));
add16 u2_add16(.a (a[31:16]),.b (b[31:16]),.cin (1'b0),.sum (sum_2),.cout ());
add16 u3_add16(.a (a[31:16]),.b (b[31:16]),.cin (1'b1),.sum (sum_3),.cout());
assign sum[31:16]=cout?sum_3:sum_2;
assign sum={sum[31:16],sum_1};
endmodule
模块加载项
module top_module(
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire [31:0]bin;
wire cout;
assign bin=b^{{32{sub}}};
add16 u1_add16(.a (a[15:0]),.b (bin[15:0]),.cin (sub),.sum (sum[15:0]),.cout (cout));
add16 u2_add16(.a (a[31:16]),.b (bin[31:16]),.cin (cout),.sum (sum[31:16]),.cout ());
endmodule分块1
module top_module(
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign=a&b;
always @(*)
//begin
out_alwaysblock=a&b;
//end
endmoduleAlwaysblock2
module top_module(
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff );
assign out_assign=a^b;
always@(*) out_always_comb=a^b;
always @(posedge clk) out_always_ff=a^b;
endmoduleAlways if
module top_module(
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always );
assign out_assign=(sel_b1&sel_b2==1)?b:a;
always@(*)
begin
if(sel_b1&sel_b2==1)
out_always=b;
else
out_always=a;
end
endmoduleAlways_if2
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving ); //
always @(*) begin
if (cpu_overheated)
shut_off_computer = 1;
else if(~cpu_overheated)
shut_off_computer = 0;
end
always @(*) begin
if (~arrived)
keep_driving = ~gas_tank_empty;
else
keep_driving = 0;
end
endmoduleAlways case
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out );//
always@(*) begin // This is a combinational circuit
case(sel)
3'b0:out=data0;
3'b1:out=data1;
3'b10:out=data2;
3'b11:out=data3;
3'b100:out=data4;
3'b101:out=data5;
default:out=1'b0;
endcase
end
endmoduleAlways case2
注：casez是指忽略in中的z位
module top_module (
input [3:0] in,
output reg [1:0] pos );
always@(*)begin
casez(in)
4'bzzz1:pos=2'd0;
4'bzz10:pos=2'd1;
4'bz100:pos=2'd2;
4'b1000:pos=2'd3;
default:pos=0;
endcase
end
endmoduleAlways casez
module top_module (
input [7:0] in,
output reg [2:0] pos );
always@(*)begin
casez(in)
8'bzzzzzzz1:pos=3'd0;
8'bzzzzzz1z:pos=3'd1;
8'bzzzzz1zz:pos=3'd2;
8'bzzzz1zzz:pos=3'd3;
8'bzzz1zzzz:pos=3'd4;
8'bzz1zzzzz:pos=3'd5;
8'bz1zzzzzz:pos=3'd6;
8'b1zzzzzzz:pos=3'd7;
default:pos=0;
endcase
end
endmoduleAlways nolatches
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up );
always@(*)begin
up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
case(scancode)
16'he06b:left=1'b1;
16'he072:down=1'b1;
16'he074:right=1'b1;
16'he075:up=1'b1;
endcase
end
endmoduleConditional
module top_module (
input [7:0] a, b, c, d,
output [7:0] min);//
wire [7:0]mi,m,n;
always@(*)begin
mi<=a<b?a:b;
m<=mi<c?mi:c;
n<=m<d?m:d;
end
assign min=n;
// assign intermediate_result1 = compare? true: false;
endmodule
Reduction
& a[3:0] // AND: a[3]&a[2]&a[1]&a[0]. Equivalent to (a[3:0] == 4'hf) | b[3:0] // OR: b[3]|b[2]|b[1]|b[0]. Equivalent to (b[3:0] != 4'h0) ^ c[2:0] // XOR: c[2]^c[1]^c[0]
module top_module (
input [7:0] in,
output parity);
assign parity=^in[7:0];
endmoduleGates 100
module top_module(
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and=&in[99:0];
assign out_or=|in[99:0];
assign out_xor=^in[99:0];
endmoduleVector100r
module top_module(
input [99:0] in,
output [99:0] out
);
integer i;
always@(*)begin
for(i=0;i<100;i++)
out[i]=in[99-i];
end
endmodule
Popcount255
module top_module(
input [254:0] in,
output reg[7:0] out );
integer i;
always@(*)begin
out=8'b0;
for(i=0;i<255;i++)
out=out+in[i];
end
endmodule
Adder100i
Mt2015q4
module top_module (input x, input y, output z);
wire out_1,out_2,a,b;
assign out_1=(x^y)&x;
assign out_2=~(x^y);
assign a=out_1|out_2;
assign b=out_1&out_2;
assign z=a^b;
endmodule
Ringer
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign ringer = ~vibrate_mode & ring;
assign motor = vibrate_mode & ring;
endmodule
Thermostat
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater=mode&too_cold;
assign aircon=(~mode)&too_hot;
assign fan=heater|aircon|fan_on;
endmodulePopcount3
module top_module(
input [2:0] in,
output reg[1:0] out );
integer i;
always@(*)
begin
out=2'b0;
for(i=0;i<=2;i++)
out+=in[i];
end
endmoduleGatesv
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
assign out_both=in[2:0]&in[3:1];
assign out_any=in[3:1]|in[2:0];
assign out_different={in[3]^in[0],in[2:0]^in[3:1]};
endmoduleGatesv100
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
assign out_both=in[98:0]&in[99:1];
assign out_any=in[99:1]|in[98:0];
assign out_different={in[99]^in[0],in[99:1]^in[98:0]};
endmodule
Mux2to1
module top_module(
input a, b, sel,
output out );
assign out=sel?b:a;
endmodule
Mux2to1v
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
assign out=sel?b:a;
endmodule
Mux9to1v
module top_module(
input [15:0] a, b, c, d, e, f, g, h, i,
input [3:0] sel,
output reg[15:0] out );
always@(*)begin
case(sel)
4'd0:out=a;
4'd1:out=b;
4'd2:out=c;
4'd3:out=d;
4'd4:out=e;
4'd5:out=f;
4'd6:out=g;
4'd7:out=h;
4'd8:out=i;
default:out=16'hffff;
endcase
end
endmodule
Mux256to1
module top_module(
input [255:0] in,
input [7:0] sel,
output out );
//integer i;
//assign i=sel;
assign out=in[sel];
endmoduleMux256to1v
注：不能写成 **out=in[4*sel+3:4*sel]**;括号里的范围得是常量
module top_module(
input [1023:0] in,
input [7:0] sel,
output [3:0] out );
assign out={in[4*sel+3],in[4*sel+2],in[4*sel+1],in[4*sel]};
endmoduleHadd
module top_module(
input a, b,
output cout, sum );
assign {cout,sum}=a+b;
endmodule
Fadd
module top_module(
input a, b, cin,
output cout, sum );
assign {cout,sum}=a+b+cin;
endmoduleAdder3
module top_module(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
adder1 u_add1(
.a (a[0]),
.b (b[0]),
.cin (cin),
.cout (cout[0]),
.sum (sum[0])
);
adder1 u_add2(
.a (a[1]),
.b (b[1]),
.cin (cout[0]),
.cout (cout[1]),
.sum (sum[1])
);
adder1 u_add3(
.a (a[2]),
.b (b[2]),
.cin (cout[1]),
.cout (cout[2]),
.sum (sum[2])
);
endmodule
module adder1( input a,
input b,
input cin,
output cout,
output sum);
assign sum = a ^ b ^ cin;
assign cout= a & cin | b & cin | a & b;
endmodule
Exams/m2014 q4j
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum);
assign sum=x+y;
endmodule
Exams/ace241 q1c
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
assign s=a+b;
assign overflow = a[7] & b[7] & ~s[7] | ~a[7] & ~b[7] & s[7];
// assign s = ...
// assign overflow = ...
endmoduleadder100
module top_module(
input [99:0] a, b,
input cin,
output cout,
output [99:0] sum );
assign {cout,sum}=a+b+cin;
endmodule
Bcdadd4
module top_module(
input [15:0] a, b,
input cin,
output cout,
output [15:0] sum );
wire [2:0]cout_1;
bcd_fadd u1_bcd_fadd(
.a (a[3:0]),
.b (b[3:0]),
.cin (cin),
.cout (cout_1[0]),
.sum (sum[3:0])
);
bcd_fadd u2_bcd_fadd(
.a (a[7:4]),
.b (b[7:4]),
.cin (cout_1[0]),
.cout (cout_1[1]),
.sum (sum[7:4])
);
bcd_fadd u3_bcd_fadd(
.a (a[11:8]),
.b (b[11:8]),
.cin (cout_1[1]),
.cout (cout_1[2]),
.sum (sum[11:8])
);
bcd_fadd u4_bcd_fadd(
.a (a[15:12]),
.b (b[15:12]),
.cin (cout_1[2]),
.cout (cout),
.sum (sum[15:12])
);
endmodule
Kmap1
module top_module(
input a,
input b,
input c,
output out );
assign out=a|b|c;
endmoduleKmap2
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out= ~a & ~d | ~b & ~c | b & c & d | a & c & d;
endmodule
Kmap3
......
Dff
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q );//
always@(posedge clk)
q<=d;
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
endmoduleDff8
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always@(posedge clk)
q<=d;
endmoduleDff8r
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always@(posedge clk)
begin
if(reset)
q=0;
else
q<=d;
end
endmoduleDff8p
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always@(negedge clk)
begin
if(reset)
q<=16'h0x34;
else
q<=d;
end
endmoduledff8ar
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always@(posedge clk or posedge areset)
begin
if(areset)
q<=0;
else
q<=d;
end
endmoduleDff16e
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always@(posedge clk )
begin
if(!resetn)
q<=0;
else
case(byteena)
2'b00:q<=q;
2'b01:q<={q[15:8],d[7:0]};
2'b10:q<={d[15:8],q[7:0]};
2'b11:q<=d;
endcase
end
endmodule
Exams/2014 q4a
module top_module (
input d,
input ena,
output q);
always@(*)
begin
if(ena)
q<=d;
else
q<=q;
end
endmodule
Exams/2014 q4b
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q);
always@(posedge clk or posedge ar)
begin
if(ar)
q<=0;
else
q<=d;
end
endmoduleExams/2014 q4c
module top_module (
input clk,
input d,
input r, // synchronous reset
output q);
always@(posedge clk)
begin
if(r)
q<=0;
else
q<=d;
end
endmoduleExams/2014 q4d
module top_module (
input clk,
input in,
output out);
wire q1;
always@(posedge clk)
begin
out<=q1;
end
assign q1=in^out;
endmoduleMt2015 muxdff
edgedetect
顺序问题：in变化比in_reg快
module top_module (
input clk,
input [7:0] in,
output [7:0] pedge
);
reg [7:0] in_reg;
always@(posedge clk)begin
in_reg <= in;
end
always@(posedge clk)begin
pedge <= in & ~in_reg;
end
endmodule
edgedetect2
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0]store;
always@(posedge clk)
begin
store<=in;
end
always@(posedge clk)
begin
anyedge<=store^in;
end
endmodule
Edgecapture
检测到一次边沿下降后保持
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
reg [31:0]store;
always @(posedge clk)
store<=in;
always @(posedge clk)
begin
if(reset)
out<=0;
else
out<=store&(~in)|out;
end
endmodule
Dualedge(难）
module top_module (
input clk,
input d,
output q
);
reg q1,q2;
always@(negedge clk)
q1<=q2^d;
always@(posedge clk)
q2<=q1^d;
assign q=q2^q1;
endmoduleCount15
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q);
always@(posedge clk)
begin
if(reset)
q<=0;
else if(!reset)
q<=q+1;
else if(&q)
q<=0;
end
endmodule
count10
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q);
always@(posedge clk)
begin
if(reset)
q<=0;
else if(q[3]&q[0])
q<=0;
else
q<=q+1;
end
endmodulecount1~10
module top_module (
input clk,
input reset,
output reg [3:0] q);
always@(posedge clk)
begin
if(reset)
q<=4'b1;
else if(q[3]&q[1]&(~q[0])&(~q[2]))
q<=4'b1;
else
q<=q+1;
end
endmoduleCountslow
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q);
always@(posedge clk)
begin
if(reset)
q<=4'b0;
else if(slowena)
begin
if(q==4'b1001)
begin
q<=4'b0;
end
else begin
q<=q+1'b1;
end
end
endExams/ece241 2014 q7a
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
assign c_enable = enable;
assign c_load = reset | ((Q == 4'd12) && enable == 1'b1);
assign c_d = c_load ? 4'd1 : 4'd0;
count4 the_counter (clk, c_enable, c_load, c_d,Q );
endmodule Exams/ece241 2014 q7b
(****)
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
); //
wire [3:0]one,ten,hundred;
assign c_enable={(ten==4'd9&&one==4'd9),one==4'd9,1'b1};
assign OneHertz=(one==4'd9)&(ten==4'd9)&(hundred==4'd9);
bcdcount counter0 (clk, reset, c_enable[0],one);
bcdcount counter1 (clk, reset, c_enable[1],ten);
bcdcount counter2 (clk, reset, c_enable[2],hundred);
endmodule
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q);
wire one,ten,houndred,thousand;
alway@(posedge clk)
if(reset)
q<=0;
else begin
q[3:0]<=q[3:0]+1;
if(q[3:0]>4'd9)begin
ena[1]<=1;
q[3:0]<=0;
end
endmodule
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q);
wire one,ten,houndred,thousand;
alway@(posedge clk)begin
if(reset)
q<=0;
else begin if(q[3:0]>4'd9)
q[3:0]<=0;
else
q[3:0]<=q[3:0]+1;
end
end
assign ena[1]=(q[3:0]==4'd9)?1'b1:1'b0;
endmodule
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