【HDLBits刷题笔记】Exams/ece241 2013 q4

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于 2022-10-13 12:08:35 首次发布

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【HDLBits刷题笔记】Exams/ece241 2013 q4
在这里插入图片描述
Also include an active-high synchronous reset that resets the state machine to a state equivalent to if the water level had been low for a long time (no sensors asserted, and all four outputs asserted).

下面是第一种写法，按状态机的思路写的，引入了记录上一次状态的寄存器，画状态图的时候上一状态可以作为输入。代码写得这么飘逸，不确定能不能综合。

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
); 

parameter				BELOW_S1 = 0;
parameter				BETWEEN_S2_S1 = 2;
parameter				BETWEEN_S3_S2 = 4;
parameter				ABOVE_S3 = 5;

reg [3:0]				state,next_state,last_state;

always@(posedge clk) begin
	if(reset) begin
		state <= BELOW_S1;
	end
	else begin
		state <= next_state;
		last_state <= state;
	end
end

always@(*) begin
	case(state)