仲裁器---总线仲裁器（CPU自制）

下面是一个总线仲裁的逻辑和简单tb，实际参考网上常见的那一个版本，但是有点问题纠正一下。
http://blog.eetop.cn/blog-317611-13565.html

//以输入信号作为状态机的转移条件，写得比较冗余
//优先级排序ABC
// 总线上挂3个信号A,B,C，仲裁信号grant[1:0]。
// grant[1:0]=2’b00   A获得总线
// grant[1:0]=2’b01   B获得总线
// grant[1:0]=2’b10   C获得总线
// 总线轮询算法a.如果当前只有一个信号请求，则处理.
// b.如果没有请求，那么A获得总线.
// c.如果同时有多个信号请求，考虑上一个请求信号，
// 如果上一个请求信号是A，那么轮询的是BCA，
// 如果上一个请求信号是B，那么轮询的是CAB，
// 如果上一个请求信号是C，那么轮询的是ABC
//
`resetall
`timescale 1ns/10ps
module bus_arbitor(clk, rst_n, signal_a, signal_b, signal_c, grant);
// I/O definition
input      clk;
input      rst_n;
input      signal_a;
input      signal_b;
input      signal_c;
output   [1:0] grant;
// register definition
reg   [1:0] grant;
reg  [1:0] ls;
// parameter definition
parameter   s_null = 3'b000,
            s_a    = 3'b001,
            s_b    = 3'b010,
            s_c    = 3'b100,
            s_ab   = 3'b110,
            s_bc   = 3'b011,
            s_ac   = 3'b101,
            s_abc  = 3'b111;
//module part and FSM
always @(posedge clk or negedge rst_n)
if(!rst_n)// bus disable when negtive rst_n
begin
grant <= 2'b11;
//cs <= s_null;
ls <= s_null;
end
else
begin
case({signal_a, signal_b, signal_c})// bus enable with FSM
  s_null:
     begin
        grant <= 2'b00;
        ls <= s_a;
     end
  s_a:
     begin
        grant <= 2'b00;
        ls <= s_a;          //?
     end
  s_b:
     begin
        grant <= 2'b01;
        ls <= s_b;
     end
  s_c:
     begin
        grant <= 2'b10;
        ls <= s_c;
     end
  s_ab:
     case(ls)// feedback MUX configured
        s_a: begin grant <= 2'b01; ls <= s_b;end
        s_b: begin grant <= 2'b00; ls <= s_a; end
        s_c: begin grant <= 2'b00; ls <= s_a; end
        default:begin grant <= 2'b00; ls <= s_a;end
     endcase
  s_bc:
     case(ls)
        s_a: begin grant <= 2'b01; ls <= s_b; end
        s_b: begin grant <= 2'b10; ls <= s_c; end
        s_c: begin grant <= 2'b01; ls <= s_b; end
        default:begin grant <= 2'b00; ls <= s_a;end
     endcase
  s_ac:
     case(ls)
        s_a: begin grant <= 2'b10; ls <= s_c; end
        s_b: begin grant <= 2'b10; ls <= s_c; end
        s_c: begin grant <= 2'b00; ls <= s_a; end
        default:begin grant <= 2'b00; ls <= s_a; end
     endcase
  s_abc:
     case(ls)
        s_a: begin grant <= 2'b01; ls <= s_b; end
        s_b: begin grant <= 2'b10; ls <= s_c; end
        s_c: begin grant <= 2'b00; ls <= s_a; end
        default:begin grant <= 2'b00; ls <= s_a; end
     endcase
  default:
  begin grant <= 2'b00; ls <= s_a; end
            
endcase
end
endmodule