VL13 时钟分频(偶数)
话不多说,直接看波形就知道了
rtl代码
`timescale 1ns / 1ps
module even_div
(
input wire rst ,
input wire clk_in,
output wire clk_out2,
output wire clk_out4,
output wire clk_out8
);
//*************code***********//
reg out2;
reg out4;
reg out8;
always @(posedge clk_in or negedge rst) begin
if(rst == 1'b0)
out2 <= 1'b0;
else
out2 <= ~out2;
end
always @(posedge out2 or negedge rst) begin
if(rst == 1'b0)
out4 <= 1'b0;
else
out4 <= ~out4;
end
always @(posedge out4 or negedge rst) begin
if(rst == 1'b0)
out8 <= 1'b0;
else
out8 <= ~out8;
end
assign clk_out2 = out2;
assign clk_out4 = out4;
assign clk_out8 = out8;
//*************code***********//
endmodule
tesstbench 代码
`timescale 1ns / 1ps
module even_div_tb();
reg rst ;
reg clk_in;
wire clk_out2;
wire clk_out4;
wire clk_out8;
even_div even_div01(
.rst(rst),
.clk_in(clk_in),
.clk_out2(clk_out2),
.clk_out4(clk_out4),
.clk_out8(clk_out8)
);
real CYCLE_200MHz = 5 ;
initial begin
rst=0;clk_in=0;
#5 rst=1;clk_in=1;
#5 rst=1;clk_in=0;
#5 rst=1;clk_in=1;
#5 rst=1;clk_in=0;
#5 rst=1;clk_in=1; #5 rst=1;clk_in=0;
#5 rst=1;clk_in=1; #5 rst=1;clk_in=0;
#5 rst=1;clk_in=1; #5 rst=1;clk_in=0;
#5 rst=1;clk_in=1; #5 rst=1;clk_in=0;
#5 rst=1;clk_in=1; #5 rst=1;clk_in=0;
#5 rst=1;clk_in=1; #5 rst=1;clk_in=0;
#5 rst=1;clk_in=1; #5 rst=1;clk_in=0;
#5 rst=1;clk_in=1; #5 rst=1;clk_in=0;
#5 rst=1;clk_in=1; #5 rst=1;clk_in=0;
#5 rst=1;clk_in=1;
$stop;
end
endmodule