状态机这章题目比较多,分个小章节记录一下。
1.Simple FSM1
题目:
This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.
This exercise is the same as fsm1s, but using asynchronous reset.
思路:
第一题用来熟悉摩尔状态机的写法,题目把组合逻辑模块和时序逻辑模块都给好了,往里面填东西就行了。
代码:
module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output out);//
parameter A=0, B=1;
reg state, next_state;
always @(*) begin // This is a combinational always block
// State transition logic
case({state,in})
A:next_state = in ? A:B;
B: next_steta = in ? B:A;
endcase
end
always @(posedge clk, posedge areset) begin // This is a sequential always block
// State flip-flops with asynchronous reset
if(areset)
state <= B;
else
state <= next_state;
end
// Output logic
// assign out = (state == ...);
assign out = (state==B);
endmodule
组合模块用来更新下一个状态,时序模块用来复位以及给更新当前状态。
Moore状态机的输出只由当前状态决定,与输入无关。
Mealy状态机的输出与当前状态和输入均有关。
2.Simple FSM1
题目:
This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.
This exercise is the same as fsm1, but using synchronous reset.
思路:
与题1类似,不同的是本题改为同步复位。而且题目给的模板是一段式。
代码:
// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
parameter A=0,B=1;
reg present_state, next_state;
always @(posedge clk) begin
if (reset) begin
// Fill in reset logic
present_state <= B;
out <= 1;
end else begin
case (present_state)
// Fill in state transition logic
A: next_state = in ? A:B;
B: next_state = in ? B:A;
endcase
// State flip-flops
present_state = next_state;
case (present_state)
// Fill in output logic
A: out = 0;
B: out = 1;
endcase
end
end
endmodule
一开始输出一直不匹配,才发现在复位判断内没有给输出out赋值。这算是三段式和一段式的一个注意事项吧。
3.Simple FSM2
题目:
This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.
This exercise is the same as fsm2s, but using asynchronous reset.
思路:
题目给出了一个JK触发器,包含2个输入J、K,一个输出out,异步复位,代码为三段式。与题1思路类似。
代码:
module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
OFF: next_state = j ? ON:OFF;
ON : next_state = k ? OFF:ON;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if(areset)
state <= OFF;
else
state <= next_state;
end
// Output logic
// assign out = (state == ...);
assign out = (state == ON);
endmodule
4.Simple FSM 2
题目:
This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.
This exercise is the same as fsm2, but using synchronous reset.
思路:
与题3一样的JK触发器,同步复位,三段式复刻。
代码:
module top_module(
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
ON : next_state = k ? OFF:ON;
OFF : next_state = j ? ON:OFF;
endcase
end
always @(posedge clk) begin
// State flip-flops with synchronous reset
if(reset)
state <= OFF;
else
state <= next_state;
end
// Output logic
// assign out = (state == ...);
assign out = (state == ON);
endmodule
5.Simple state transitions 3(FSM3comb)
题目:
The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following state encoding: A=2'b00, B=2'b01, C=2'b10, D=2'b11.
Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. Given the current state (state
), compute the next_state
and output (out
) based on the state transition table.
State | Next state | Output | |
in=0 | in=1 | ||
A | A | B | 0 |
B | C | B | 0 |
C | A | D | 0 |
D | C | B | 1 |
思路:
要求根据状态转换表设计状态机的组合逻辑模块和输出模块,考虑用case枚举4个状态。
代码:
module top_module(
input in,
input [1:0] state,
output [1:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
always@(*) begin
case(state)
A: next_state = in? B:A;
B: next_state = in? B:C;
C: next_state = in? D:A;
D: next_state = in? B:C;
endcase
end
assign out = (state==D);
endmodule
6.Simple one-hot state transitions 3(FSM3onehot)
题目:
The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000.
Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. (The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).
State | Next state | Output | |
in=0 | in=1 | ||
A | A | B | 0 |
B | C | B | 0 |
C | A | D | 0 |
D | C | B | 1 |
思路:
独热码状态转换,由于该编码只有一个状态位为1,因此可以仅检查一个状态位来更新下一个状态。
代码:
module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[0] = (state[0]&~in)|(state[2]&~in);
assign next_state[1] = (state[0]&in)|(state[1]*in)|(state[3]&in);
assign next_state[2] = (state[1]&~in)|(state[3]&~in);
assign next_state[3] = state[2]∈
// Output logic:
assign out = state[3]? 1:0;
endmodule
7.Simple FSM 3(FSM3)异步复位
题目:
See also: State transition logic for this FSM
The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.
State | Next state | Output | |
in=0 | in=1 | ||
A | A | B | 0 |
B | C | B | 0 |
C | A | D | 0 |
D | C | B | 1 |
思路:
跟前面几题的状态转换表没有什么变化,注意的是复位使状态变为A。
代码:
module top_module(
input clk,
input in,
input areset,
output out); //
parameter A=0,B=1,C=2,D=3;
reg [1:0] state,next_state;
// State transition logic
always@(*) begin
case(state)
A: next_state = in? B:A;
B: next_state = in? B:C;
C: next_state = in? D:A;
D: next_state = in? B:C;
endcase
end
// State flip-flops with asynchronous reset
always@(posedge clk,posedge areset) begin
if(areset)
state <= A;
else
state <= next_state;
end
// Output logic
assign out = (state==D);
endmodule
8.Simple FSM3 (FSM3s) 同步复位
题目:
See also: State transition logic for this FSM
The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.)
思路:
整体与题7类似,不同的是复位方式为同步复位。
代码:
module top_module(
input clk,
input in,
input reset,
output out); //
parameter A=0,B=1,C=2,D=3;
reg [1:0] state,next_state;
// State transition logic
always@(*) begin
case(state)
A: next_state = in? B:A;
B: next_state = in? B:C;
C: next_state = in? D:A;
D: next_state = in? B:C;
endcase
end
// State flip-flops with asynchronous reset
always@(posedge clk) begin
if(reset)
state <= A;
else
state <= next_state;
end
// Output logic
assign out = (state==D);
endmodule
9.Design a Moore FSM(Exams/ece241 2013 q4)
题目:
思路:
题目要求设计一个判断水位以及水流开关的状态机。
一共有4个水位,S3,S2,S1以及低于S1,这里我假设为S0
当水位为S3时,表示为111,对应水流开关为000
水位为S2时,表示为011,对应水流开关为001
水位为S1时,表示为001,对应水流开关为011
水位为S0时,表示为000,对应水流开关为111
此外还有一个判断水位变化的标识dfr,当当前水位低于前一时刻的水位时,dfr为1,否则为0。
(两个时刻水位相同时,根据答案反推应该是dfr<=dfr)
由于水位肯定是渐近变化的,即只能从S0->S1->S2->S3,或者S3->S2->S1->S0,
不存在如S0->S2这类变化。
这里我用了3个时序逻辑与1个组合逻辑来实现题目要求的功能,状态变量为4个(ABCD)。
(理论上时序逻辑只需要1个,用来实现复位操作以及将下一个时刻状态赋值给当前时刻;
组合逻辑数目任意,这里是为了区分开每个模块的功能而使用了多个always块)
代码:
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
parameter A=0,B=1,C=3,D=7;
reg [2:0]state,next_state;
reg [2:0] out;
assign {fr3,fr2,fr1} = out;
always@(*) begin
case(s)
3'b000: next_state = A;
3'b001: next_state = B;
3'b011: next_state = C;
3'b111: next_state = D;
default: next_state = A;
endcase
end
always@(posedge clk) begin
if(reset) begin
state<=A;
end
else begin
state<=next_state;
end
end
always@(posedge clk) begin
if(reset) begin
out <= 3'b111;
end
else begin
case(next_state)
A: out <= 3'b111;
B: out <= 3'b011;
C: out <= 3'b001;
D: out <= 3'b000;
endcase
end
end
always@(posedge clk) begin
if(reset) begin
dfr <= 1;
end
else begin
if(next_state<state)
dfr <= 1;
else if(next_state>state)
dfr <= 0;
else
dfr <= dfr;
end
end
endmodule
官方答案:
module top_module (
input clk,
input reset,
input [3:1] s,
output reg fr3,
output reg fr2,
output reg fr1,
output reg dfr
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
// We have 6 states here.
parameter A2=0, B1=1, B2=2, C1=3, C2=4, D1=5;
reg [2:0] state, next; // Make sure these are big enough to hold the state encodings.
// Edge-triggered always block (DFFs) for state flip-flops. Synchronous reset.
always @(posedge clk) begin
if (reset) state <= A2;
else state <= next;
end
// Combinational always block for state transition logic. Given the current state and inputs,
// what should be next state be?
// Combinational always block: Use blocking assignments.
always@(*) begin
case (state)
A2: next = s[1] ? B1 : A2;
B1: next = s[2] ? C1 : (s[1] ? B1 : A2);
B2: next = s[2] ? C1 : (s[1] ? B2 : A2);
C1: next = s[3] ? D1 : (s[2] ? C1 : B2);
C2: next = s[3] ? D1 : (s[2] ? C2 : B2);
D1: next = s[3] ? D1 : C2;
default: next = 'x;
endcase
end
// Combinational output logic. In this problem, a procedural block (combinational always block)
// is more convenient. Be careful not to create a latch.
always@(*) begin
case (state)
A2: {fr3, fr2, fr1, dfr} = 4'b1111;
B1: {fr3, fr2, fr1, dfr} = 4'b0110;
B2: {fr3, fr2, fr1, dfr} = 4'b0111;
C1: {fr3, fr2, fr1, dfr} = 4'b0010;
C2: {fr3, fr2, fr1, dfr} = 4'b0011;
D1: {fr3, fr2, fr1, dfr} = 4'b0000;
default: {fr3, fr2, fr1, dfr} = 'x;
endcase
end
endmodule
官方解法定义了6个状态,A2,B1,B2,C1,C2,D1。
因为最高水位S3和最低水位S0只有2种变化可能(S3只可能与S2发生转换,S0则是与S1,来回2次),而中间水位S1与S2有4种,因此可以根据变化的可能定义状态。
第二个always块中,根据当前状态state与输入s预测下一时刻的状态。
由于4个水位分别为111,011,001,000。与独热码的思路类似,只需要考虑输入s的某1-2位就可以预测下一时刻的状态。
官方答案比较直观的一点在于,定义了6个状态,用字母A-D表示水位状态S,用数字1、2分别表示与前一时刻的水位是否发生了变化,1表示从低到高,2表示从高到低。(第三个always块)