触发器的最后一题,答案解法有点不好理解。
题干:
You're familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list.
Build a circuit that functionally behaves like a dual-edge triggered flip-flop:
难点:FPGA中没有双边沿触发器,因此不能在always块中直接使用"posedge clk or negedge clk"的写法。
按题目提示分别构造两个触发器(上升沿触发和下降沿触发)。
解法1:
module top_module (
input clk,
input d,
output q
);
reg q1,q2;
always@(posedge clk) begin
q1<=d;
end
always@(negedge clk) begin
q2<=d;
end
assign q = clk?q1:q2;
endmodule
该解法比较直观,但是可能出现毛刺。
关于毛刺产生的原因:FPGA中如何实现双边沿采样?_李锐博恩的博客-CSDN博客_双沿采样
法1最后在输出q时用了三目运算符,如果改写成
assign q = ( clk&q1 ) | (~clk & q2);
当q1和q2同时为1时,就是 q=clk+~clk,不知道可不可以把毛刺产生原因理解为竞争冒险?
解法2:
官方解法。
module top_module(
input clk,
input d,
output q);
reg p, n;
// A positive-edge triggered flip-flop
always @(posedge clk)
p <= d ^ n;
// A negative-edge triggered flip-flop
always @(negedge clk)
n <= d ^ p;
// Why does this work?
// After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.
// After negedge clk, n changes to d^p. Thus q = (p^n) = (p^d^p) = d.
// At each (positive or negative) clock edge, p and n FFs alternately
// load a value that will cancel out the other and cause the new value of d to remain.
assign q = p ^ n;
// Can't synthesize this.
/*always @(posedge clk, negedge clk) begin
q <= d;
end*/
endmodule