MTBF的解析,MTBF分为几种测试方法

一、MTBF预测法 1、相关标准,目前用于MTBF预计计算的主要标准为MIL-HDBK-217F,对应国内版本为G J B 2 9 9 B。该标准为美军的可靠性预计手册,用于MTBF的预计计算。该标准从95年发布最后一版后不再对其进行更新维护,这本身也反应了标准本身的局限性。 2、预计法的局限性,MIL-HDBK-217F采用了应力分析法和元件计数法分析产品的MTBF。该方法通过元器件的数量以及零件的故障率评估产品的无故障时间。这种方法假设了产品的器件都工作在预期的工作应力下,实际上由于不可预期的因素,产品
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一、MTBF预测法 1、相关标准,目前用于MTBF预计计算的主要标准为MIL-HDBK-217F,对应国内版本为G J B 2 9 9 B。该标准为美军的可靠性预计手册,用于MTBF的预计计算。该标准从95年发布最后一版后不再对其进行更新维护,这本身也反应了标准本身的局限性。 2、预计法的局限性,MIL-HDBK-217F采用了应力分析法和元件计数法分析产品的MTBF。该方法通过元器件的数量以及零件的故障率评估产品的无故障时间。这种方法假设了产品的器件都工作在预期的工作应力下,实际上由于不可预期的因素,产品可能会有瞬间的过应力。另外还有一种情况就是部分对产品寿命有影响的应力难以评估周全。没有充分考虑产品的生产工艺、人为因素对产品可靠性的影响。同时在计算参数的选择上受计算人员对系数的掌握和了解程度影响很大,因此和实际值相比会有很大的差异。 3、基本公式及参数 Failure rate=λp = λb πEπQπCπSπAπLπT λb:零件基础失效率 πE 环境因素Environment factor) πQ 品质因素:(Quality factor) πA 应用因素:(Application factor) πC 复杂性因素:(Quality factor) πL 累计因素:(Learning factor) πS 电应力因素:(Electrical Stress factor) πT 温度因素:(Temperature factor) 这种方法最大的优势是可以在有限的时间里完成对产品MTBF值的较准确预估。
二、MTBF试验法 1、试验方法,实验方式主要有:全寿命试验、定时截尾试验、定数截尾试验。全寿命试验要求所有样品都在试验中最终都失效,只需要采用简单的算术平均值就可以计算出MTBF。但事实上需要试验样品在试验过程中全部失效,所需要的试验时间可能长大几年、十几年甚至上百年,因此此方法只可能使用于产品的寿命时

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MIL-HDBK-217F, Notice 1 is issued to correct minor typographical errors in the basic F Revision. MIL HDBK-217F(base document) provides the following changes based upon recently completed studies (see Ret 30 and 32 listed in Appendix C) 1. New failure rate prediction models are provided for the following nine major classes of microcircuits Monolithic Bipolar Digital and Linear Gate/Logic Array Devices Monolithic MOS Digital and Linear Gate/Logic Array Devices Monolithic Bipolar and MOS Digital Microprocessor Devices(Including Controllers Monolithic Bipolar and Mos Memory Devices Monolithic GaAs Digital Devices Monolithic GaAs MMIC Devices Hybrid Microcircuits Magnetic Bubble Memories Surface Acoustic Wave Devices This revision provides new prediction models for bipolar and Mos microcircuits with gate counts up to 60,000, linear microcircuits with up to 3000 transistors, bipolar and Mos digital microprocessor and co- processors up to 32 bits, memory devices with up to 1 million bits, GaAs monolithic microwave integrated circuits(MMICs)with up to 1,000 active elements, and GaAs digital ICs with up to 10,000 transistors. The C, factors have been extensively revised to reflect new technology devices with improved reliability, and the activation energies representing the temperature sensitivity of the dice(IT)have been changed for MOS devices and for memories. The Ca factor remains unchanged from the previous Handbook version, but includes pin grid arrays and surlace mount packages using the same model as hermetic, solder-sealed dual in-line packages. New values have been included for the quality factor (o), the learning factor(i, and the environmental factor(aE). The model for hybrid microcircuits has been revised to be simpler to use, to delete the temperature dependence of the seal and interconnect fallure rate contributions, and to provide a method of calculating chip junction temperatures 2. A new model for Very High Speed Integrated Circuits(VHSIC/HSIC Like)and very Large Scale Integration(VLSi)devices (gate counts above 60, 000 3. The reformatting of the entire handbook to make i easier to use. 4. A reduction in the number of environmental factors( F)from 27 to 14 5. A revised fallure rate model for Network Resistors 6. Revised models for TWTs and Klystrons based on data supplied by the Electronic Industries Association Microwave Tube Division Supersedes page vil of Revision F A1emn彐TTu"“11r4raeK
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