阶段二设计

最新推荐文章于 2024-01-28 19:48:47 发布

HYL_2015

最新推荐文章于 2024-01-28 19:48:47 发布

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分类专栏：科技文章标签：设计

本文链接：https://blog.csdn.net/HYL_2015/article/details/74532350

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该博客主要探讨了阶段二设计中涉及的两个关键部分：一是实现多周期的恒最大值计数及显示电路，二是通过调节LED亮度进行0到9的循环计数，其中0表示最低亮度，9表示最高亮度。

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2-1：多周期-恒最大值计数-显示电路
这里写图片描述

module cnt_synt(CLK, CNT, OV);
input CLK ;
output reg[31:0] CNT;
output reg OV ;
parameter MAX_VAL = 50_000_000;
always @ (posedge CLK) begin
if(CNT < MAX_VAL)
    CNT <= CNT+ 1'b1 ;
else
    CNT <= 0;
end
always @ (CNT) begin
 if (CNT==MAX_VAL)
 OV = 1'b1;
 else
 OV = 1'b0;
end
endmodule

module cnt_0to9(CLK, EN, IN,OUT);
input CLK, EN ;
output reg [7:0] OUT;
output reg [3:0] IN ;
always @ (posedge CLK ) begin
  if(EN) begin
    if(IN < 9)
    IN <= IN + 1'b1 ;
    else
    IN <= 0;
  end 
  else
  IN <= IN ;
end
always @ (IN) begin
    case(IN)
    4'h0: OUT = 8'b1100_0000;
    4'h1: OUT = 8'b1111_1001;
    4'h2: OUT = 8'b1010_0100;
    4'h3: OUT = 8'b1011_0000;
    4'h4: OUT = 8'b1001_1001;
    4'h5: OUT = 8'b1001_0010;
    4'h6: OUT = 8'b1000_0010;
    4'h7: OUT = 8'b1111_1000;
    4'h8: OUT = 8'b1000_0000;
    4'h9: OUT = 8'b1001_0000;
    endcase
end
endmodule

![singletap波形图](https://img-blog.csdn.net/20170706114602121?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvSFlMXzIwMTU=/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/SouthEast)

``

这里写图片描述

2-2：LED的亮度调节
2-2RTL图

module cnt_synt(CLK, CNT,OV);
input CLK ;
output reg[31:0]CNT;
output reg OV;
parameter MAX_VAL=500_000;
always @ (posedge CLK) begin
  if(CNT < MAX_VAL)
  CNT <= 1'b1+CNT ;
  else
  CNT <= 0;
end
always @ (CNT) begin
if (CNT == MAX_VAL )
OV = 1'b1;
else
OV = 1'b0;
end
endmodule
module duty_division(CLK, EN, OUT);
input CLK ,EN;
output reg [3:0] OUT ;
reg [7:0]COUNT;
always @ (posedge CLK) begin
if(EN)begin
    if(COUNT<99)
    COUNT <= COUNT + 1'b1;
    else
    COUNT <= 0;

    if((COUNT >= 0)&&(COUNT <50))
    OUT[0] <= 1;
    else
    OUT[0] <=0;

    if((COUNT >= 0)&&(COUNT <25))
    OUT[1] <= 1;
    else
    OUT[1] <=0;

    if((COUNT >= 0)&&(COUNT <100/8))
    OUT[2] <= 1;
    else
    OUT[2] <=0;

    if((COUNT >= 0)&&(COUNT <100/16))
    OUT[3] <= 1;
    else
    OUT[3] <=0;
    end

else
    COUNT<= COUNT;
end
endmodule

这里写图片描述

2-3:0到9循环计数，0最暗，9最亮

这里写图片描述

module cnt_synt(CLK , CNT ,OV);
input CLK ;
output reg [31:0] CNT;
output reg OV ;
parameter MAX_VAL = 50000_000;
always @ (posedge CLK ) begin
if(CNT < MAX_VAL)
    CNT <= CNT+ 1'b1;
    else
    CNT <= 0;
end
always @(CNT) begin
if(CNT== MAX_VAL)
    OV = 1'b1;
    else
    OV = 1'b0;
end
endmodule

module cnt_en_0to9(CLK, EN ,CNT);
input CLK ,EN;
output reg [3:0]CNT ;
always @ (posedge CLK) begin
if(EN)begin
    if(CNT <9)
    CNT <= CNT+ 1'b1 ;
    else
    CNT <= 0 ;
    end
else
    CNT <= CNT;
end
endmodule

module duty_division(CLK,IN,PULSE);
input CLK ;
input [3:0]IN;
output reg PULSE ;
reg [6:0] COUNT;
always @ (posedge CLK)begin

    if(COUNT < 10 )
    COUNT <= COUNT + 1'b1;
    else
    COUNT <= 0;

    if((COUNT >= 0 )&& (COUNT <= IN))
    PULSE <= 1;
    else
    PULSE <= 0;
end
endmodule


module dec_4to7(IN,EN,OUT);
input EN ;
input [3:0]IN;
output reg[7:0] OUT;

always @(IN) begin  
if(EN) begin
case(IN)

4'h1: OUT = 8'b1111_1001;
4'h2: OUT = 8'b1010_0100;
4'h3: OUT = 8'b1011_0000;
4'h4: OUT = 8'b1001_1001;
4'h5: OUT = 8'b1001_0010;
4'h6: OUT = 8'b1000_0010;
4'h7: OUT = 8'b1111_1000;
4'h8: OUT = 8'b1000_0000;
4'h9: OUT = 8'b1001_0000;
4'h0: OUT = 8'b1100_0000;
default: OUT = 8'b1111_1111;
endcase
end
else
OUT = 8'b1111_1111;
end
endmodule