mini2440系统移植篇之u-boot第一阶段汇编

最新推荐文章于 2022-06-28 16:22:52 发布

HYQ458941968

最新推荐文章于 2022-06-28 16:22:52 发布

阅读量448

点赞数

分类专栏：嵌入式Linux系统移植

本文链接：https://blog.csdn.net/HYQ458941968/article/details/45508345

版权

嵌入式Linux系统移植专栏收录该内容

9 篇文章 0 订阅

订阅专栏

1. 第一阶段汇编

1.1. 流程图

1.1.1. 异常向量表

.globl _start
_start:	b	start_code
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_undefined_instruction:	.word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq

	.balignl 16,0xdeadbeef

1.1.2. 硬件初始化

SVC管理员模式

start_code:
	/*********** set the cpu to SVC32 mode***********/
	mrs	r0, cpsr
	bic	r0, r0, #0x1f
	orr	r0, r0, #0xd3
	msr	cpsr, r0

关看门狗和中断

/*
 *************************************************************************
 *
 * turn off the watchdog
 * 关看门狗
 *
 *************************************************************************
 */
#define pWTCON	0x53000000

	ldr	r0, =pWTCON
	mov	r1, #0x0
	str	r1, [r0]

/*
 *************************************************************************
 *
 * mask all IRQs by setting all bits in the INTMR - default
 * 关中断和子中断
 *
 *************************************************************************
 */
#define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
#define INTSUBMSK	0x4A00001C

	mov	r1, #0xffffffff
	ldr	r0, =INTMSK
	str	r1, [r0]

	ldr	r1, =0x7fff
	ldr	r0, =INTSUBMSK
	str	r1, [r0]

设置时钟频率

/*
 *************************************************************************
 *
 * 设置时钟频率
 * FCLK:HCLK:PCLK = 1:4:8
 *
 *************************************************************************
 */
#define CLKDIVN	 	0x4C000014	/* clock divisor register */
#define MPLLCON   	0x4C000004   
#define UPLLCON   	0x4C000008 
#define CAMDIVN	  	0x4C000018

	ldr	r0, =CLKDIVN          //FCLK:HCLK:PCLK = 1:4:8
	mov  r1, #5
	str	r1, [r0]

	mrc	p15, 0, r1, c1, c0, 0	
	orr	r1, r1, #0xc0000000		
	mcr	p15, 0, r1, c1, c0, 0

	ldr	r0, =CAMDIVN          
	mov  r1, #0
	str	r1, [r0]

	ldr	r0, =MPLLCON		
	ldr	r1, =0x7F021		 //405MHz  
	str	r1, [r0]

	ldr	r0, =UPLLCON		  
	ldr	r1, =0x38022		//48MHz 
	str	r1, [r0]

关MMU和cache

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
	orr	r0, r0, #0x00000002	@ set bit 1 (A) Align
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
	mcr	p15, 0, r0, c1, c0, 0

	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	mov	ip, lr

	bl	lowlevel_init

	mov	lr, ip
	mov	pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

初始化内存

.globl lowlevel_init
lowlevel_init:
	/* memory control configuration */
	/* make r0 relative the current location so that it */
	/* reads SMRDATA out of FLASH rather than memory ! */
	ldr     r0, =SMRDATA
	ldr	r1, _TEXT_BASE
	sub	r0, r0, r1
	ldr	r1, =BWSCON	/* Bus Width Status Controller */
	add     r2, r0, #13*4
0:
	ldr     r3, [r0], #4
	str     r3, [r1], #4
	cmp     r2, r0
	bne     0b

	/* everything is fine now */
	mov	pc, lr

	.ltorg
/* the literal pools origin */

SMRDATA:
    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+REFCNT)
    .word 0xb1	//==hyq - 1011 0001
    .word 0x30
    .word 0x30

1.1.3. 加载u-boot到内存

/*
 *************************************************************************
 *
 * boot from nor flash or ram but not 0x33f80000
 *
 *************************************************************************
 */
relocate:				/* relocate U-Boot to RAM	    */
	adr	r0, _start		/* r0 <- current position of code   */
	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
					/* don't reloc during debug         */
	ldr	r2, _armboot_start
	ldr	r3, _bss_start
	sub	r2, r3, r2		/* r2 <- size of armboot            */
	add	r2, r0, r2		/* r2 <- source end address         */

copy_loop:
	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end addreee [r2]    */
	ble	copy_loop

1.1.4. 初始化堆栈

/*
 *************************************************************************
 *
 * Set up the stack
 * 设置堆栈
 *
 *************************************************************************
 */
stack_setup:
	ldr	r0, _TEXT_BASE		/* upper 512 KiB: relocated uboot   */
	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area              */
	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                 */
#ifdef CONFIG_USE_IRQ
	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
	sub	sp, r0, #12		/* leave 3 words for abort-stack    */

1.1.5. 清BSS，跳到第二阶段C

/*
 *************************************************************************
 *
 * BBS清零
 *
 *************************************************************************
 */
clear_bss:
	ldr	r0, _bss_start		/* find start of bss segment        */
	ldr	r1, _bss_end		/* stop here                        */
	mov	r2, #0x00000000		/* clear                            */

clbss_l:
	str	r2, [r0]		/* clear loop...                    */
	add	r0, r0, #4
	cmp	r0, r1
	ble	clbss_l

#ifdef CONFIG_DEBUG_LL
	ldr	r1, SerBase
	ldr	r5, =STR_MAIN
	bl	PrintString
#endif

	ldr	pc, _start_armboot	//==跳入C代码

_start_armboot:	.word start_armboot

1.2. u-boot内存分别图

uboot可以烧到norflash，也可以烧到nand flash，假设放在norflash，norflash被映射到0地址空间。u-boot链接地址是0x33f80000，所以在汇编阶段，要把u-boot代码从0负责到0x33f80000地址，这是内存SDRAM的高地址区域。内存再下面是堆区，u-boot的全局数据区，中断栈，最后才是正常的栈地址sp。