1.调试的时候,发现上位机接收到的数据少了一位(考虑的上位机接收时序为下降沿接收数据所以回传数据也应该为下降沿回传)
/*******************************************************************************************/
/*******************************Host_data***************************************************/
/*******************************Company:HCTEK***********************************************/
/***************************Date??2019-05-16************************************************/
/*******************Reference protocol for Command&address&Data interaction*****************/
/*******************************************************************************************/
/*****backup_station decided the station about shake hand with HOST interference************/
/* ____________ ******/
/******\COMMAND-done/|____________| ******/
/* ____________ *****/
/*******************\ADDRESS-DONE/|____________| ___ ___ ___ ___ **/
/**********************************\mosi-signal/___| |___| |___| |___| |_________~~**/
/*******************************************************************************************/
module slave_spi(
input wire host_clk,
input wire rst_n,
input wire mosi_cs,// low vaild
input wire mosi,
output wire miso_data
);
reg [4:0] bit_cnt;
reg [15:0] trans_end_reg;
reg [4:0] State;
reg [3:0] read_back_cnt;
reg miso_reg;
wire [15:0] trans_end;
parameter IDLE =4'b0001;
parameter READ =4'b0010;
parameter READ_addr =4'b0100;
parameter READ_back_data =4'b1000;
parameter read_addr_data =16'h55af;
parameter read_command =16'h55aa;
parameter read_address =16'h0002;
parameter backup_station =4'd0; /*not fix*/
assign trans_end=trans_end_reg;
assign miso_data=miso_reg;
always@(posedge host_clk or negedge rst_n)
if(rst_n==1'd0)
bit_cnt<=0;
else if(bit_cnt==5'd15)
bit_cnt<='d0;
else if(mosi_cs==1'b0)
bit_cnt<=bit_cnt+1'b1;
always@(posedge host_clk or negedge rst_n)
if(rst_n==1'd0)
trans_end_reg<=0;
else case(bit_cnt)
5'd0: begin
trans_end_reg[0]<=mosi;
end
5'd1: begin
trans_end_reg[1]<=mosi;
end
5'd2: begin
trans_end_reg[2]<=mosi;
end
5'd3: begin
trans_end_reg[3]<=mosi;
end
5'd4: begin
trans_end_reg[4]<=mosi;
end
5'd5: begin
trans_end_reg[5]<=mosi;
end
5'd6: begin
trans_end_reg[6]<=mosi;
end
5'd7: begin
trans_end_reg[7]<=mosi;
end
5'd8: begin
trans_end_reg[8]<=mosi;
end
5'd9: begin
trans_end_reg[9]<=mosi;
end
5'd10: begin
trans_end_reg[10]<=mosi;
end
5'd11: begin
trans_end_reg[11]<=mosi;
end
5'd12: begin
trans_end_reg[12]<=mosi;
end
5'd13: begin
trans_end_reg[13]<=mosi;
end
5'd14: begin
trans_end_reg[14]<=mosi;
end
5'd15: begin
trans_end_reg[15]<=mosi;
end
default:;
endcase
always@(posedge host_clk or negedge rst_n)
if(rst_n==1'd0)
State<=IDLE;
else case(State)
IDLE: if(trans_end_reg==read_command)
State<=READ;
READ: if(trans_end_reg==read_address)
State<=READ_addr;
READ_addr: if(read_back_cnt==4'd15)
State<=READ_back_data;
READ_back_data: State<=IDLE;
default:;
endcase
always@(posedge host_clk or negedge rst_n)
if(rst_n==1'd0)
read_back_cnt<=0;
else if(read_back_cnt==4'd15)
read_back_cnt<=0;
else if(State==READ_addr)
read_back_cnt<=read_back_cnt+1'b1;
always@(negedge host_clk or negedge rst_n)
if(rst_n==1'd0)
miso_reg<=0;
else if(State==READ_addr)
case(read_back_cnt)
backup_station: begin
miso_reg<=read_addr_data[0];
end
backup_station+1: begin
miso_reg<=read_addr_data[1];
end
backup_station+2: begin
miso_reg<=read_addr_data[2];
end
backup_station+3: begin
miso_reg<=read_addr_data[3];
end
backup_station+4: begin
miso_reg<=read_addr_data[4];
end
backup_station+5: begin
miso_reg<=read_addr_data[5];
end
backup_station+6: begin
miso_reg<=read_addr_data[6];
end
backup_station+7: begin
miso_reg<=read_addr_data[7];
end
backup_station+8: begin
miso_reg<=read_addr_data[8];
end
backup_station+9: begin
miso_reg<=read_addr_data[9];
end
backup_station+10: begin
miso_reg<=read_addr_data[10];
end
backup_station+11: begin
miso_reg<=read_addr_data[11];
end
backup_station+12: begin
miso_reg<=read_addr_data[12];
end
backup_station+13: begin
miso_reg<=read_addr_data[13];
end
backup_station+14: begin
miso_reg<=read_addr_data[14];
end
backup_station+15: begin
miso_reg<=read_addr_data[15];
end
default: miso_reg<='d0;
endcase
endmodule