一、while语句;
do begin
@top_vif.mon_cb;
uvm_hdl_read("tb.DUT.done",done);
end while(done==0);
二、枚举 case语句;
typedef enum {INT,FS_INT,FS_ERR} int_type_e;
virtual task wait_signal(int_type_e int_type);
forever begin
`uvm_info("wait_int", $sformatf("Waitting int assert..."), UVM_LOW)
case(int_type)
INT: @(posedge top_vif.a);
FS_INT: @(posedge top_vif.b);
FS_ERR: @(posedge top_vif.c);
default: `uvm_error("wait_int", $sformatf("invalid int_type %s ",int_type))
endcase
`uvm_info("wait_signal", $sformatf("Int asserted..."), UVM_LOW)
@top_vif.mon_cb;
end
endtask :wait_signal
三、宏定义传参;
`define int_raw_data(index,write_data) \
if(``index``==0)begin \ reg_model.isp_be_cfg_ral.INT_RAW.write(status,``write_data``,UVM_FRONTDOOR); \
end
`int_raw_data(index,write_data)