FPGA 数字时钟，支持暂停计时、清零、置数

学习记录

功能

设计一个可以计时的数字时钟，其显示时间范围是 00:00:00~23:59:59，且该时钟具有暂停计时、清零、置数等功能。（没有数码管、为了方便显示，没有使用分频后的时钟）

框图

仿真结果

set置数

从23.59.59-0.0.0

ENA为低电平时暂停计数

计数清零

仿真文件可以在github上看到github仿真文件链接

源码

module Digital_clock (
	input clk,
	input rst_n,
	input ena,
	input set,
	input [7:0]s_hh,
	input [7:0]s_mm,
	input [7:0]s_ss,
	output  [7:0]hh,
	output  [7:0]mm,
	output  [7:0]ss
	);
	
	wire sm_c, mh_c;
	wire CLK_1Hz;
	
	Div_50 u1( .CLOCK_50(clk), .RST_n(rst_n), .ENA(1'b1), .iDIV_Cont(8'd50), .oCLK(CLK_1Hz) );
	Cont_60 u2( .clk(clk),  	.rst_n(rst_n), 	.ena(ena), 		.set(set), 	.s_sm(s_ss), 	.sm(ss), 	.carry(sm_c) );
	Cont_60 u3( .clk(sm_c), 	.rst_n(rst_n), 	.ena(1'b1), 	.set(set), 	.s_sm(s_mm), 	.sm(mm), 	.carry(mh_c) );
	Cont_24 u4( .clk(mh_c), 	.rst_n(rst_n), 	.ena(1'b1), 	.set(set), 	.s_hh(s_hh), 	.hh(hh) );
	
endmodule
//========================================================
module Div_50( CLOCK_50, RST_n, ENA, iDIV_Cont, oCLK);

input CLOCK_50;
input RST_n;
input ENA;
input [7:0] iDIV_Cont;
output oCLK;

reg oCLK_i = 1'b0;
reg [7:0] COUNTER = 8'b0;

assign oCLK = oCLK_i;

always @(posedge CLOCK_50, negedge RST_n, posedge ENA)
begin
	if(!RST_n)
	begin
		COUNTER <= 8'b0;
		end
	else if(ENA == 1'b1)
	begin
		if (COUNTER == iDIV_Cont/2 - 1'b1)
		begin
			COUNTER <= 8'b0;
			oCLK_i = ~oCLK_i;
		end
		else
			COUNTER <= COUNTER +1'b1;
	end
end

endmodule



//========================================================
module Cont_60(
	input clk,
	input rst_n,
	input ena,
	input set,
	input [7:0]s_sm,
	output reg [7:0]sm,
	output reg carry
	);
	
	always@(posedge clk, negedge rst_n, posedge set, posedge ena)
	begin
		if(!rst_n)
		begin
			sm <= 8'b0;
			carry <= 1'b0;
		end
		else if(set)
		begin
			sm <= s_sm;
			carry <= 1'b0;
		end
		else if(ena)
		begin
			if(sm == 8'd59)
			begin
				sm <= 8'b0;
				carry <= 1'b1;
			end
			else
			begin
				sm <= sm + 1'b1;
				carry <= 1'b0;
			end
		end
			
	end
	
endmodule
	
	

//========================================================
module Cont_24(
	input clk,
	input rst_n,
	input ena,
	input set,
	input [7:0]s_hh,
	output reg [7:0]hh
	);
	
	always@(posedge clk, negedge rst_n, posedge set)
	begin
		if(!rst_n)
		begin
			hh <= 8'b0;
		end
		else if(set)
		begin
			hh <= s_hh;
		end
		else if(ena)
		begin
			if(hh == 8'd23)
			begin
				hh <= 8'b0;
			end
			else
				hh <= hh + 1'b1;
		end
	end
	
endmodule

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