LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H8 IS
PORT(clk:IN STD_LOGIC;
ena:IN STD_LOGIC;
clr:IN STD_LOGIC;
led:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE CNT OF H8 IS
signal A : integer range 0 to 7;
signal B : std_logic_vector(7 downto 0);
signal C : std_logic_vector(7 downto 0);
begin
P1:process(clk,clr,ena)
begin
if clr = '0' then C <= "00000000";
elsif ena = '1'
then if clk'event and clk = '1' then A <= A + 1;
end if;
end if;
end process P1;
P2:process(A)
begin
case A is
when 0 => B <="00000001";
when 1 => B <&