--分频:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fdiv is
Port (clkin :in std_logic;
bclk:out std_logic);
end fdiv;
architecture be of fdiv is
Begin
process(clkin)
variable d0:integer range 0 to 10000000;
begin
if rising_edge(clkin) then
if (d0<10000000) then
d0:=d0+1;
else
d0:=0;
end if;
if(d0=10000000)then
bclk<='1';
else bclk<='0';
end if;
end if;
end process;
end be;
--按键消抖:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity key is
port(key,clk:in std_logic;--按键
keyout: out std_logic );
end key;
architecture one of key is
signal count:integer range 0 to 400000;
signal df1,df,res_n:std_logic;
signal df2:std_logic;
constant timer:integer:=400000;
begin
process(clk)
begin
if (clk'event and clk='1')then
df1<=key;
df2<=df1;
end if;
df<=df1 xor df2;
res_n<=df;
end process;
process(clk,res_n)
begin
if res_n='1'then
count<=0;
else
if rising_edge(clk)then
count<=count+1;
if(count=400000)then
count<=0;
end if;
if count>=timer then
keyout<=key;
end if;
end if;
end if;
end process;
end one;
--流水灯:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY lsd IS
PORT (clk,rst1:IN std_logic;
key1,key2,key3,key4:in std_logic;
led_tmp: OUT std_logic_vector(7 DOWNTO 0));
END lsd;
ARCHITECTURE lc OF lsd IS
SIGNAL tmp:std_logic_vector(3 DOWNTO 0);
SIGNAL cnt:integer range 0 to 7;
BEGIN
PROCESS(clk,rst1)
variable key:std_logic_vector(4 DOWNTO 0);
begin
key :=(key1&key2&key3&key4&rst1);
IF(clk'EVENT AND clk='1')THEN
case key is
when "01111"=>tmp<="0111";
when "10111"=>tmp<="1011";
when "11011"=>tmp<="1101";
when "11101"=>tmp<="1110";
when "11110"=>tmp<="1111";
when OTHERS =>NULL;
end case;
end if;
end process;
process(tmp,clk)
begin
if (clk'event and clk='1')then
CASE tmp is
when "1111" =>led_tmp <= "11111111";cnt<=0;
when "0111" =>CASE cnt IS
when 0 =>led_tmp<="11111110";cnt<=cnt+1;
when 1 =>led_tmp<="11111101";cnt<=cnt+1;
when 2 =>led_tmp<="11111011";cnt<=cnt+1;
when 3 =>led_tmp<="11110111";cnt<=cnt+1;
when 4 =>led_tmp<="11101111";cnt<=cnt+1;
when 5 =>led_tmp<="11011111";cnt<=cnt+1;
when 6 =>led_tmp<="10111111";cnt<=cnt+1;
when 7 =>led_tmp<="01111111";cnt<=0;
when OTHERS =>NULL;
END CASE;
when "1011" =>
CASE cnt IS
when 0 =>led_tmp<="01111111";cnt<=cnt+1;
when 1 =>led_tmp<="10111111";cnt<=cnt+1;
when 2 =>led_tmp<="11011111";cnt<=cnt+1;
when 3 =>led_tmp<="11101111";cnt<=cnt+1;
when 4 =>led_tmp<="11110111";cnt<=cnt+1;
when 5 =>led_tmp<="11111011";cnt<=cnt+1;
when 6 =>led_tmp<="11111101";cnt<=cnt+1;
when 7 =>led_tmp<="11111110";cnt<=0;
when OTHERS =>NULL;
END CASE;
when "1101" =>
CASE cnt IS
when 0 =>led_tmp<="00111111";cnt<=cnt+1;
when 1 =>led_tmp<="10011111";cnt<=cnt+1;
when 2 =>led_tmp<="11001111";cnt<=cnt+1;
when 3 =>led_tmp<="11100111";cnt<=cnt+1;
when 4 =>led_tmp<="11110011";cnt<=cnt+1;
when 5 =>led_tmp<="11111001";cnt<=cnt+1;
when 6 =>led_tmp<="11111100";cnt<=cnt+1;
when 7 =>led_tmp<="01111110";cnt<=0;
when OTHERS =>NULL;
END CASE;
when "1110" =>
CASE cnt IS
when 0 =>led_tmp<="10001111";cnt<=cnt+1;
when 1 =>led_tmp<="11100011";cnt<=cnt+1;
when 2 =>led_tmp<="11111000";cnt<=cnt+1;
when 3 =>led_tmp<="00011111";cnt<=cnt+1;
when 4 =>led_tmp<="11000111";cnt<=cnt+1;
when 5 =>led_tmp<="11110001";cnt<=cnt+1;
when 6 =>led_tmp<="11111000";cnt<=cnt+1;
when 7 =>led_tmp<="11100011";cnt<=0;
when OTHERS =>NULL;
END CASE;
when OTHERS =>NULL;
END CASE;
END IF;
end process;
end lc;
--主体:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lsd_led is
port(clk,rst:in std_logic;
keya,keyb,keyc,keyd:in std_logic;
led_out:out std_logic_vector(7 DOWNTO 0));
end;
architecture a of lsd_led is
signal clk1,L1,L2,L3,L4:std_logic;
component fdiv is
Port (clkin :in std_logic;
bclk:out std_logic);
end component;
component key is
port(key,clk:in std_logic;--按键
keyout: out std_logic );
end component;
component lsd IS
PORT (clk,rst1:IN std_logic;
key1,key2,key3,key4:in std_logic;
led_tmp: OUT std_logic_vector(7 DOWNTO 0));
END component;
begin
U1:fdiv port map(clk,clk1);
U2:key port map(keya,clk,L1);
U3:key port map(keyb,clk,L2);
U4:key port map(keyc,clk,L3);
U5:key port map(keyd,clk,L4);
U6:lsd port map(clk1,rst,L1,L2,L3,L4,led_out);
end a;
--分频:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fdiv is
Port (clkin :in std_logic;
bclk:out std_logic);
end fdiv;
architecture be of fdiv is
Begin
process(clkin)
variable d0:integer range 0 to 10000000;
begin
if rising_edge(clkin) then
if (d0<10000000) then
d0:=d0+1;
else
d0:=0;
end if;
if(d0=10000000)then
bclk<='1';
else bclk<='0';
end if;
end if;
end process;
end be;
--按键消抖:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity key is
port(key,clk:in std_logic;--按键
keyout: out std_logic );
end key;
architecture one of key is
signal count:integer range 0 to 400000;
signal df1,df,res_n:std_logic;
signal df2:std_logic;
constant timer:integer:=400000;
begin
process(clk)
begin
if (clk'event and clk='1')then
df1<=key;
df2<=df1;
end if;
df<=df1 xor df2;
res_n<=df;
end process;
process(clk,res_n)
begin
if res_n='1'then
count<=0;
else
if rising_edge(clk)then
count<=count+1;
if(count=400000)then
count<=0;
end if;
if count>=timer then
keyout<=key;
end if;
end if;
end if;
end process;
end one;
--流水灯:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY lsd IS
PORT (clk,rst1:IN std_logic;
key1,key2,key3,key4:in std_logic;
led_tmp: OUT std_logic_vector(7 DOWNTO 0));
END lsd;
ARCHITECTURE lc OF lsd IS
SIGNAL tmp:std_logic_vector(3 DOWNTO 0);
SIGNAL cnt:integer range 0 to 7;
BEGIN
PROCESS(clk,rst1)
variable key:std_logic_vector(4 DOWNTO 0);
begin
key :=(key1&key2&key3&key4&rst1);
IF(clk'EVENT AND clk='1')THEN
case key is
when "01111"=>tmp<="0111";
when "10111"=>tmp<="1011";
when "11011"=>tmp<="1101";
when "11101"=>tmp<="1110";
when "11110"=>tmp<="1111";
when OTHERS =>NULL;
end case;
end if;
end process;
process(tmp,clk)
begin
if (clk'event and clk='1')then
CASE tmp is
when "1111" =>led_tmp <= "11111111";cnt<=0;
when "0111" =>CASE cnt IS
when 0 =>led_tmp<="11111110";cnt<=cnt+1;
when 1 =>led_tmp<="11111101";cnt<=cnt+1;
when 2 =>led_tmp<="11111011";cnt<=cnt+1;
when 3 =>led_tmp<="11110111";cnt<=cnt+1;
when 4 =>led_tmp<="11101111";cnt<=cnt+1;
when 5 =>led_tmp<="11011111";cnt<=cnt+1;
when 6 =>led_tmp<="10111111";cnt<=cnt+1;
when 7 =>led_tmp<="01111111";cnt<=0;
when OTHERS =>NULL;
END CASE;
when "1011" =>
CASE cnt IS
when 0 =>led_tmp<="01111111";cnt<=cnt+1;
when 1 =>led_tmp<="10111111";cnt<=cnt+1;
when 2 =>led_tmp<="11011111";cnt<=cnt+1;
when 3 =>led_tmp<="11101111";cnt<=cnt+1;
when 4 =>led_tmp<="11110111";cnt<=cnt+1;
when 5 =>led_tmp<="11111011";cnt<=cnt+1;
when 6 =>led_tmp<="11111101";cnt<=cnt+1;
when 7 =>led_tmp<="11111110";cnt<=0;
when OTHERS =>NULL;
END CASE;
when "1101" =>
CASE cnt IS
when 0 =>led_tmp<="00111111";cnt<=cnt+1;
when 1 =>led_tmp<="10011111";cnt<=cnt+1;
when 2 =>led_tmp<="11001111";cnt<=cnt+1;
when 3 =>led_tmp<="11100111";cnt<=cnt+1;
when 4 =>led_tmp<="11110011";cnt<=cnt+1;
when 5 =>led_tmp<="11111001";cnt<=cnt+1;
when 6 =>led_tmp<="11111100";cnt<=cnt+1;
when 7 =>led_tmp<="01111110";cnt<=0;
when OTHERS =>NULL;
END CASE;
when "1110" =>
CASE cnt IS
when 0 =>led_tmp<="10001111";cnt<=cnt+1;
when 1 =>led_tmp<="11100011";cnt<=cnt+1;
when 2 =>led_tmp<="11111000";cnt<=cnt+1;
when 3 =>led_tmp<="00011111";cnt<=cnt+1;
when 4 =>led_tmp<="11000111";cnt<=cnt+1;
when 5 =>led_tmp<="11110001";cnt<=cnt+1;
when 6 =>led_tmp<="11111000";cnt<=cnt+1;
when 7 =>led_tmp<="11100011";cnt<=0;
when OTHERS =>NULL;
END CASE;
when OTHERS =>NULL;
END CASE;
END IF;
end process;
end lc;
--主体:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lsd_led is
port(clk,rst:in std_logic;
keya,keyb,keyc,keyd:in std_logic;
led_out:out std_logic_vector(7 DOWNTO 0));
end;
architecture a of lsd_led is
signal clk1,L1,L2,L3,L4:std_logic;
component fdiv is
Port (clkin :in std_logic;
bclk:out std_logic);
end component;
component key is
port(key,clk:in std_logic;--按键
keyout: out std_logic );
end component;
component lsd IS
PORT (clk,rst1:IN std_logic;
key1,key2,key3,key4:in std_logic;
led_tmp: OUT std_logic_vector(7 DOWNTO 0));
END component;
begin
U1:fdiv port map(clk,clk1);
U2:key port map(keya,clk,L1);
U3:key port map(keyb,clk,L2);
U4:key port map(keyc,clk,L3);
U5:key port map(keyd,clk,L4);
U6:lsd port map(clk1,rst,L1,L2,L3,L4,led_out);
end a;