VIVADO报错记录

报错1：[DRC PDRC-43] PLL_adv_ClkFrequency_div_no_dclk: The computed value 200.000 MHz (CLKIN1_PERIOD, net clk_out1) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X1Y1 (cell top_dual_ov5640_hdmi10/u_ddr3_top/u_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/plle2_i) falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1866.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (20.000000), multiplication factor CLKFBOUT_MULT_F (4) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

报错原因：设置的时钟频率超出例化器件的工作频率范围

解决方案：检查时钟ip所分配的时钟的时钟是否正确。

报错2[Synth 8-3438] module 'key_debounce' declared at 'E:/Vinci_test/verilog/key_debounce.v:1' does not have any parameter 'CNT_MAX1' used as named parameter override ["E:/Vinci_test/verilog/lcd_rgb_char.v":368]

报错原因：常量如果在顶层模块和其他模块的值不一样，会使用顶层模块里面的值。或常量名不一致所导致的

解决方案：检查常量名是否一致，localparameter更改为parameter