Cortex-M4的组件层次梳理与NIVC

---

前言

---

下面内容可供参考，如有错误请指正。

1 Cortex-M4的不同层次

1.1 main interface

根据下图，Cortex-M4处理器支持两个层次结构进行集成或实现：①processor component level,处理器组件级，②CORTEXM4integration level, 集成级，CORTEXM4INTEGRATION.

CORTEXM4 component level，contains the basic processor. This level includes optional components, configurable to your requirements. In particular, the floating point component is included at this level, if it is present. See Floating point support on page 2-5. Y ou must not modify the CORTEXM4 component level RTL code.

CORTEXM4组件级别包含基本处理器。此级别包括可根据您的需求配置的可选组件。特别是，如果存在浮点组件，则在该级别包含该组件。您不能修改CORTEXM4组件级RTL代码。

CORTEXM4INTEGRATION level,Instantiates the Cortex-M4 processor component level and provides example integration with the Cortex-M4 Debug Access Port (DAP), Wakeup Interrupt Controller (WIC), Embedded Trace Macrocell (ETM) and Trace Port Interface Unit (TPIU). This level is provided as a working example of a single-processor sub-system. You can modify it to suit your requirements.

CORTEXM4INTEGRATION level:实例化Cortex-M4处理器组件级别，并提供了与Cortex-M4调试访问端口(DAP)、唤醒中断控制器(WIC)、嵌入式跟踪宏单元(ETM)和跟踪端口接口单元(TPIU)集成的示例。这个级别是作为一个单处理器子系统的工作示例提供的。可以修改它以满足要求。为了优化低功耗设计，NVIC集成了睡眠模式，包括一个可选的深度睡眠功能。这使得整个设备快速关闭，同时仍然保持程序状态。

也就是说，我们的例化或者设计的修改，应该在此level下，从而满足设计要求。

1.2 Integration kit

The integration kit contains these levels:•cm4ik_cortexm4integration_timing level• cm4ik_sys level • CM4IKMCU level • tbench level .
cm4ik_cortexm4integration_timing level
This level instantiates the CORTEXM4INTEGRATION level.This level delays all inputs to the CORTEXM4INTEGRATION level to support netlist simulations with timing.**
cm4ik_sys level
This section describes the cm4ik_sys level and its components. The cm4ik_sys level contains:cm4ik_cortexm4integration_timing level,CPIO0,GPIO1,GPIO2,AHB default slave,AHB ROM Memory,SRAM and SRAM controller,AHB bus interconnect,Miscellaneous logic,System level ROM table.

所以，对于处理器系统的更改，例如添加flash之类的东西，可以在sys level这一层进行。然后通过CMSDK生成bus matrix。

2 组件介绍

接下来是组件的介绍，第一部分介绍组要的组件，其中先说处理器级别的 再说处理器系统（虚线框是可选的配置），第二部分主要是NVIC的有关内容。

The Cortex-M4 processor includes a low gate count processor core with low latency interrupt processing,an optional Floating Point Unit (FPU), a Nested Vectored Interrupt Controller (NVIC), and otherfeatures.

2.1主要组件

第一是处理器的组件，Process core、FPU等。
接下来是可选的配置，ETM等。

2.2 NVIC

NVIC是置于处理器内的组件，与内核相连，Nested Vectored Interrupt Controller，NVIC是一种支持低延迟中断处理的嵌入式中断控制器。它负责全部中断相关的操作，比如说中断优先级判断，现场保护与恢复，中断使能等等。NVIC 提供了一组寄存器，我们将通过 NVIC 寄存器对它进行设置。根据寄存器的不同配置，进行不同的关于中断的操作。

手册中提到的NVIC的特点如下：

Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low-latency interrupt processing. Features include:
— External interrupts, configurable from 1 to 240.
— Bits of priority, configurable from 3 to 8.
— Dynamic reprioritization of interrupts.
— Priority grouping. This enables selection of preempting interrupt levels and non preempting interrupt levels.
— Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt
processing without the overhead of state saving and restoration between interrupts.
— Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead.
— Optional Wake-up Interrupt Controller (WIC), providing ultra-low-power sleep mode support.

2.2.1 NVIC寄存器整理

NVIC包括8类寄存器，85+601+1+1=102个，每个32bits。每个复位值0x00000000。
（还有新添加的ICTR Interrupt Controller Type Register 所以103个，这里只是一个大致的整理。具体可以参考手册

**ICTR ** Interrupt Controller Type Register 中断控制器类型寄存器
Shows the number of interrupt lines that the NVIC supports.显示NVIC支持的中断行数。

ISER 中断使能寄存器
Enables, or reads the enable state of a group of interrupts.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority.If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority。
enable有效的情况下pending的interrupt才回被启用，不然的话disable时pending的interrupt不会被启用
ICER Interrupt Clear-Enable Registers 中断清除使能寄存器

Disables, or reads the enable state of, a group of registers.

ISPR Interrupt Set-Pending Registers 中断挂起寄存器
ICPR Interrupt Clear-Pending Registers
IABR Interrupt Active Bit Registers
IPR Interrupt Priority Registers

3 与中断有关的其他寄存器

STIR
Software Trigger Interrupt Register 软件触发中断寄存器
Provides a mechanism for software to generate an interrupt.
指示要触发的中断。写入的值为(ExceptionNumber - 16)
写入这个寄存器的效果与将中断对应的NVIC ISPR位设置为1相同

VTOR
Vector Table Offset Register
Holds the vector table address.保存向量表地址


AIRCR

Application Interrupt and Reset Control Register 应用中断和复位控制寄存器

总结

例如：本文简单介绍关于M4的一些整理,不算是很全面，后面依然会一点一点加上来，没有提及的部分或错误地方，先感谢指正。 最后，ctrl+S保平安...