一种实现RAM的最简单方式,可以被vivado综合为ram,而非寄存器组:
(* ram_style="block" *)reg [7:0] mem [0:15] ;
always@(posedge sys_clk) begin
mem[addr] <= din ;
end
always@(posedge sys_clk or posedge rst) begin
if(rst) dout <= 8'd0 ;
else begin
dout <= mem[addr] ;
end
end