硬件电路设计基础

Mr.Pentium

已于 2024-01-15 23:12:41 修改

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分类专栏：硬件电路设计基础文章标签：硬件工程

于 2024-01-15 11:29:35 首次发布

本文链接：https://blog.csdn.net/Pentium6666/article/details/135594077

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DC-DC(Direct Current)

一、芯片外围电路设计

在这里插入图片描述

链接：参考芯片信号：TMI3253SH

①可调电阻

Alt
$\frac{V{\tiny FB} }{R{\tiny 2}} =\frac{V{\scriptsize out} }{R{\tiny 1} +R{\tiny 2} } \tag{1}$
$R{\scriptsize 2} =\frac{R{\scriptsize 1} }{V{\tiny OUT} /V{\tiny FB} -1} \tag{2}$

通过调整外围电阻R1,R2的比值，来设定Vout；
前馈电容Cfb ,一般都是pF级别,能够帮助DC-DC内部环路更稳定，原理上就是给系统函数H(s)各增加一个零点、一个极点。

②电感

$L=\frac{V{\scriptsize out} \times (V{\scriptsize in} -V{\scriptsize out} )}{V{\scriptsize in} \times \bigtriangleup I{\scriptsize L} \times f{\scriptsize osc} } \tag{3}$

$I{\scriptsize L{\scriptsize (MAX)}} =I{\scriptsize LOAD} + \frac{\triangle I{\scriptsize L} }{2} \tag{4}$

ΔIL is the inductor ripple current（纹波电流）. Choose inductor ripple current to be approximately 30% if the maximum load current, 3A；
A 1.0μH to 4.7μH inductor with a DC current rating of at least 25% percent higher than the maximum load current is recommended for most applications.
Fosc（开关频率），根据设定来进行代值计算；

③输出电容

Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The output voltage ripple can be estimated by:
$Detail:\bigtriangleup V{\scriptsize out} =\frac{V{\scriptsize out} }{fs\times L } \times \left [ 1- \frac{V{\scriptsize out} }{V{\scriptsize in} } \right ]\times \left [R{\scriptsize ESR} + \frac{1}{8\times fs\times C{\scriptsize out} } \right ] \tag{5}$
In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated by:
$Simple:\bigtriangleup V{\scriptsize out} = \frac{Vout}{8\times f^{2} s\times L \times C{\scriptsize out} } \times \left [ 1- \frac{V{\scriptsize out} }{V{\scriptsize in} } \right ] \tag{6}$
$\Rightarrow C{\scriptsize out} =\frac{V{\scriptsize out} }{8\times f^{2} s\times L\times \bigtriangleup V{\scriptsize out} } \times \left [ 1-\frac{V{\scriptsize out} }{V{\scriptsize in} } \right ] \tag{7}$

通常Cout一般会采用并联的形式，常见操作是“大电容”并联“小电容”（100nF左右）的方式，前者滤低频，后者滤高频。并联Cout的两个原因：不同值、不同封装的电容能够拓宽滤波频带；并联能够使Resr更小，进而纹波更小。
一般实际选取的数值是理论计算值的2倍，当然仿真＋实际验证一下是最好的。

④输入电容

$dc=\frac{V{\scriptsize out} }{V{\scriptsize in} \times \eta } \tag{8}$
$C{\scriptsize min} =\frac{I{\scriptsize out} \times dc\times (1-dc)\times 1000}{f{\scriptsize sw} \times V{\scriptsize P(MAX)} } \tag{9}$