Chapter 13 Reduced Instruction Set Computer

1. Key features
   • Limited and simple instructions set with a fixed format
   • Large number of general purpose registers or use of compiler technology to optimize register use
   • Emphasis on optimizing the instruction pipeline
2. Instruction execution characteristics
3. The use of a large register file
   • Register features
   • • Faster than cache, memory
     • Shorter address
     • Near CPU
   • Software solution
   • • Require compiler to allocate registers
     • Allocate based on most used variables in a given time
     • Requires sophisticated program analysis
   • Hardware solution
   • • Have more registers
     • Thus more variables will be in registers
   • Registers for local variables
   • • Store local scalar variables in registers
     • Reduces memory access
     • Every procedure(function) call changes locality
     • • Parameters must be passed
       • Results myst be returned
     • Variables from calling programs must be stored to registers
   • Register Windows
   • • Typically, a procedure employs:
     • • Only few parameters and local variables
       • Limited range of depth of call
     • Use multiple small sets of registers, each assigned to a different procedure
     • • a window for a procedure
     • Calls switch to a different set of registers, rather than saving contents of registers into memory
     • Windows for adjacent procedures are overlapped to allow parameter passing
     • Returns switch back to a previously used set of registers
     • Global variables: allocated by the compiler to memory
     • Compiler based register optimization: optimization is done by the RISC compiler
     • • Assign symbolic or virtual register to each candidate variable
       • Graph coloring: to decide which variables can use registers at any given point in a program
       • • The nodes are symbolic registers, if two symbolic registers are "live" during the same program fragment, they are joined by a edge to depict interference
         • Try to color the graph with n colors, where n is the number of real registers
         • • Colors represents the number of physical registers
           • The same color means the same register
         • If this process does not fully succeed, then those nodes that cannot be colored must be placed in memory
4. Reduced instruction set architecture
   • Charateristics
   • • One instruction per cycle
     • Register to register operations
     • Few, simple addressing modes
     • Few, simple, fixed instruction formats
     • Hardwired design
     • Effectively instruction pipelining
     • More responsive to interrupt
     • More compile time/effort
5. RISC vs CISC
   • Compiler simplification
   • • To compile less machine instructions(Hard to find the exactly fit instructions)
     • Smaller & faster programs
6. RISC pipelining
   • Most instructions are register to register
   • Two phases of execution
   • • I: Instruction fetch
     • E: Execute
   • For load and store, three phases are required:
   • • I: Instruction fetch
     • E: Execute
     • • Calculate memory address
     • D: Memory
     • • Register to memory or memory to register operation
     • Delay slot