经过半个月的实习终于有时间再把这个半成品搞一搞了。通过今天的调试u-boot终于有输出了,以下是调试过程:
一,修改start . S,这里我没有删除源码中任何一行代码,只是把要删除的注释掉了,大家看的时候要仔细了
/*
* armboot - Startup Code for ARM1176 CPU-core
*
* Copyright (c) 2007 Samsung Electronics
*
* Copyright (C) 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
* 2007-09-21 - Added MoviNAND and OneNAND boot codes by
* jsgood (jsgood.yang@samsung.com)
* Base codes by scsuh (sc.suh)
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#ifdef CONFIG_ENABLE_MMU
#include <asm/proc/domain.h>
#endif
#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#endif
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_start: b reset
#ifndef CONFIG_NAND_SPL
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction:
.word undefined_instruction
_software_interrupt:
.word software_interrupt
_prefetch_abort:
.word prefetch_abort
_data_abort:
.word data_abort
_not_used:
.word not_used
_irq:
.word irq
_fiq:
.word fiq
_pad:
.word 0x12345678 /* now 16*4=64 */
#else
. = _start + 64
#endif
.global _end_vect
_end_vect:
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*
*************************************************************************
*/
.globl _TEXT_BASE
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
/*
* Below variable is very important because we use MMU in U-Boot.
* Without it, we cannot run code correctly before MMU is ON.
* by scsuh.
*/
_TEXT_PHY_BASE:
.word CONFIG_SYS_PHY_UBOOT_BASE
/*
* These are defined in the board-specific linker script.
* Subtracting _start from them lets the linker put their
* relative position in the executable instead of leaving
* them null.
*/
.globl _bss_start_ofs
_bss_start_ofs:
.word __bss_start - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end__ - _start
.globl _end_ofs
_end_ofs:
.word _end - _start
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual reset code
*/
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0, cpsr
bic r0, r0, #0x3f
orr r0, r0, #0xd3
msr cpsr, r0
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
cpu_init_crit:
/*
* When booting from NAND - it has definitely been a reset, so, no need
* to flush caches and disable the MMU
*/
#ifndef CONFIG_NAND_SPL
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
/* Prepare to disable the MMU */
adr r2, mmu_disable_phys
sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
b mmu_disable
.align 5
/* Run in a single cache-line */
mmu_disable:
mcr p15, 0, r0, c1, c0, 0
nop
nop
mov pc, r2
mmu_disable_phys:
#ifdef CONFIG_DISABLE_TCM
/*
* Disable the TCMs
*/
mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
cmp r0, #0
beq skip_tcmdisable
mov r1, #0
mov r2, #1
tst r0, r2
mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
tst r0, r2, LSL #16
mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
skip_tcmdisable:
#endif
#endif
#ifdef CONFIG_PERIPORT_REMAP
/* Peri port setup */
ldr r0, =CONFIG_PERIPORT_BASE
orr r0, r0, #CONFIG_PERIPORT_SIZE
mcr p15,0,r0,c15,c2,4
#endif
/*
* Go setup Memory and board specific bits prior to relocation.
*/
bl lowlevel_init /* go setup pll,mux,memory */
/* Set stackpointer in internal RAM to call board_init_f */
//call_board_init_f:
// ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
// bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
// ldr r0,=0x00000000
// bl board_init_f
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
*/
.globl relocate_code
relocate_code:
#ifndef CONFIG_NAND_SPL
mov sp, #(1024*8)
mov r0, #0
ldr r1, =_start
ldr r2, _bss_end_ofs
bl copy_to_ddr
#endif
/* mov r4, r0 /* save addr_sp */
/* mov r5, r1 /* save addr of gd *//*
mov r6, r2 /* save addr of destination */
/* Set up the stack */
/*stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
/* mov r1, r6 /* r1 <- scratch for copy_loop */
/* ldr r3, _bss_start_ofs
/* add r2, r0, r3 /* r2 <- source end address */
/*copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
/* stmia r1!, {r9-r10} /* copy to target address [r1] */
/* cmp r0, r2 /* until source end address [r2] */
/* blo copy_loop
#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
/* ldr r0, _TEXT_BASE /* r0 <- Text base */
/* sub r9, r6, r0 /* r9 <- relocation offset */
/* ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
/* add r10, r10, r0 /* r10 <- sym table in FLASH */
/* ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
/* add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
/* ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
/* add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
/*fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
/* add r0, r0, r9 /* r0 <- location to fix up in RAM */
/* ldr r1, [r2, #4]
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
/* beq fixrel
cmp r7, #2 /* absolute fixup? */
/* beq fixabs
/* ignore unknown type of fixup */
/* b fixnext
fixabs:
/* absolute fix: set location to (offset) symbol value */
/* mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
/* add r1, r10, r1 /* r1 <- address of symbol in table */
/* ldr r1, [r1, #4] /* r1 <- symbol value */
/* add r1, r1, r9 /* r1 <- relocated sym addr */
/* b fixnext
fixrel:
/* relative fix: increase location by offset */
/* ldr r1, [r0]
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
/* cmp r2, r3
blo fixloop
#endif
#ifdef CONFIG_ENABLE_MMU
enable_mmu:
/* enable domain access */
/* ldr r5, =0x0000ffff
mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
/* Set the TTB register */
/* ldr r0, _mmu_table_base
ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
ldr r2, =0xfff00000
bic r0, r0, r2
orr r1, r0, r1
mcr p15, 0, r1, c2, c0, 0
/* Enable the MMU */
/* mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #1 /* Set CR_M to enable MMU */
/* Prepare to enable the MMU */
/* adr r1, skip_hw_init
and r1, r1, #0x3fc
ldr r2, _TEXT_BASE
ldr r3, =0xfff00000
and r2, r2, r3
orr r2, r2, r1
b mmu_enable
.align 5
/* Run in a single cache-line */
/*mmu_enable:
mcr p15, 0, r0, c1, c0, 0
nop
nop
mov pc, r2
skip_hw_init:
#endif */
clear_bss:
#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
//mov r4, r6 /* reloc addr */
ldr r4, =_start
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
clbss_l:cmp r0, r1 /* clear loop... */
bhs clbss_e /* if reached end of bss, exit */
str r2, [r0]
add r0, r0, #4
b clbss_l
clbss_e:
/*#ifndef CONFIG_NAND_SPL
bl coloured_LED_init
bl red_led_on
#endif */
#endif
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
#ifdef CONFIG_NAND_SPL
ldr pc, _nand_boot
_nand_boot: .word nand_boot
#else
/* ldr r0, _board_init_r_ofs
adr r1, _start
add lr, r0, r1
add lr, lr, r9
/* setup parameters for board_init_r */
/* mov r0, r5 /* gd_t */
/* mov r1, r6 /* dest_addr */
/* jump to it ... */
/* mov pc, lr
_board_init_r_ofs:
.word board_init_r - _start */
ldr sp,=0x60000000
ldr pc, =run_in_ddr
run_in_ddr:
mov r0, #0
bl board_init_f /* 单板相关的初始化,比如初始化串口 */
#endif
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
#ifdef CONFIG_ENABLE_MMU
_mmu_table_base:
.word mmu_table
#endif
#ifndef CONFIG_NAND_SPL
/*
* we assume that cache operation is done before. (eg. cleanup_before_linux())
* actually, we don't need to do anything about cache if not use d-cache in
* U-Boot. So, in this function we clean only MMU. by scsuh
*
* void theLastJump(void *kernel, int arch_num, uint boot_params);
*/
#ifdef CONFIG_ENABLE_MMU
.globl theLastJump
theLastJump:
mov r9, r0
ldr r3, =0xfff00000
ldr r4, _TEXT_PHY_BASE
adr r5, phy_last_jump
bic r5, r5, r3
orr r5, r5, r4
mov pc, r5
phy_last_jump:
/*
* disable MMU stuff
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
mov r0, #0
mov pc, r9
#endif
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
*/
.macro bad_save_user_regs
/* carve out a frame on current user stack */
sub sp, sp, #S_FRAME_SIZE
/* Save user registers (now in svc mode) r0-r12 */
stmia sp, {r0 - r12}
ldr r2, IRQ_STACK_START_IN
/* get values for "aborted" pc and cpsr (into parm regs) */
ldmia r2, {r2 - r3}
/* grab pointer to old stack */
add r0, sp, #S_FRAME_SIZE
add r5, sp, #S_SP
mov r1, lr
/* save sp_SVC, lr_SVC, pc, cpsr */
stmia r5, {r0 - r3}
/* save current stack into r0 (param register) */
mov r0, sp
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
/* save caller lr in position 0 of saved stack */
str lr, [r13]
/* get the spsr */
mrs lr, spsr
/* save spsr in position 1 of saved stack */
str lr, [r13, #4]
/* prepare SVC-Mode */
mov r13, #MODE_SVC
@ msr spsr_c, r13
/* switch modes, make sure moves will execute */
msr spsr, r13
/* capture return pc */
mov lr, pc
/* jump to next instruction & switch modes. */
movs pc, lr
.endm
.macro get_bad_stack_swi
/* space on current stack for scratch reg. */
sub r13, r13, #4
/* save R0's value. */
str r0, [r13]
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
/* save caller lr in position 0 of saved stack */
str lr, [r0]
/* get the spsr */
mrs r0, spsr
/* save spsr in position 1 of saved stack */
str lr, [r0, #4]
/* restore r0 */
ldr r0, [r13]
/* pop stack entry */
add r13, r13, #4
.endm
/*
* exception handlers
*/
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
software_interrupt:
get_bad_stack_swi
bad_save_user_regs
bl do_software_interrupt
.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
.align 5
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif /* CONFIG_NAND_SPL */
二,在arch/arm/cpu/arm1176中添加nand拷贝文件nand_copy.c,并修改相应的makefile
#define MEM_SYS_CFG (*((volatile unsigned long *)0x7E00F120))
#define NFCONF (*((volatile unsigned long *)0x70200000))
#define NFCONT (*((volatile unsigned long *)0x70200004))
#define NFCMD (*((volatile unsigned long *)0x70200008))
#define NFADDR (*((volatile unsigned long *)0x7020000C))
#define NFDATA (*((volatile unsigned char *)0x70200010))
#define NFSTAT (*((volatile unsigned long *)0x70200028))
#define NAND_ENABLE() NFCONT &= ~(1<<1)
#define NAND_DISABLE() NFCONT |= (1<<1)
#define NAND_CMD(x) NFCMD = (x)
#define NAND_ADDR(x) NFADDR= (x)
#define NAND_GET_DATA() NFDATA
#define NAND_PUT_DATA(x) NFDATA = (x)
#define NAND_WAIT() while((NFSTAT & 0x01) == 0)
#define TACLS 0
#define TWRPH0 2
#define TWRPH1 2
void cp_nand_reset(void)
{
NAND_ENABLE();
NAND_CMD(0xff);
NAND_WAIT();
NAND_DISABLE();
}
void cp_nand_init(void)
{
MEM_SYS_CFG &= ~(1<<1);
NFCONF &= ~((1<<30) | (7<<12) | (7<<8) | (7<<4));
NFCONF |= ((TACLS<<12) | (TWRPH0<<8) | (TWRPH1<<4));
/* 使能nand flash controller */
NFCONT |= 1;
NFCONT &= ~(1<<16); /* 森止soft lock */
cp_nand_reset();
}
void cp_nand_send_addr(unsigned int addr)
{
#if 0
unsigned int page = addr / 4096;
unsigned int colunm = addr & (4096 - 1);
/* 这两个地址表示从页内哪里开始 */
NAND_ADDR(colunm & 0xff);
NAND_ADDR((colunm >> 8) & 0xff);
/* 下面三个地址表示哪一页 */
NAND_ADDR(page & 0xff);
NAND_ADDR((page >> 8) & 0xff);
NAND_ADDR((page >> 16) & 0xff);
#else
NAND_ADDR(addr & 0xff); /* a0~a7 */
NAND_ADDR((addr >> 8) & 0x0f); /* 程序的角度: a8~a11 */
NAND_ADDR((addr >> 12) & 0xff); /* 程序的角度: a12~a19 */
NAND_ADDR((addr >> 20) & 0xff); /* 程序的角度: a20~a27 */
NAND_ADDR((addr >> 28) & 0x7); /* 程序的角度: a28 ~ */
#endif
}
void cp_nand_read(unsigned int nand_start, unsigned int ddr_start, unsigned int len)
{
unsigned int addr = nand_start;
int i = nand_start % 4096;
int count = 0;
unsigned char *dest = (unsigned char *)ddr_start;
NAND_ENABLE();
while(count < len)
{
NAND_CMD(0x00);
cp_nand_send_addr(addr);
NAND_CMD(0x30);
NAND_WAIT();
for(i = 0; i < 4096 && count < len; i++)
{
if(addr < 1024*16)
{
if(i < 1024*2)
dest[count++] = NAND_GET_DATA();
}
else
{
dest[count++] = NAND_GET_DATA();
}
addr++;
}
}
NAND_DISABLE();
}
void copy_to_ddr(unsigned int nand_start, unsigned int ddr_start, unsigned int len)
{
cp_nand_init();
cp_nand_read(nand_start, ddr_start, len);
}
三,修改boad.c文件,这个文件只要修改两个函数里面的内容,我就直接把补丁文件给大家看看吧
diff -urN myuboot/u-boot-2012.07/arch/arm/lib/board.c LQuboot/u-boot-2012.07/arch/arm/lib/board.c
--- myuboot/u-boot-2012.07/arch/arm/lib/board.c 2012-07-31 02:24:37.000000000 +0800
+++ LQuboot/u-boot-2012.07/arch/arm/lib/board.c 2012-09-01 20:53:11.000000000 +0800
@@ -52,6 +52,7 @@
#include <fdtdec.h>
#include <post.h>
#include <logbuff.h>
+#include <asm/arch/s3c6400.h>
#ifdef CONFIG_BITBANGMII
#include <miiphy.h>
@@ -272,6 +273,10 @@
ulong reg;
#endif
+ GPMCON_REG = 0x1111;
+ GPMPUD_REG = 0x55;
+ GPMDAT_REG = 0x0;
+
bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
/* Pointer is writable since we allocated a register for it */
@@ -307,6 +312,7 @@
}
#endif
+
debug("monitor len: %08lX\n", gd->mon_len);
/*
* Ram is setup, size stored in gd !!
@@ -326,6 +332,7 @@
gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
#endif
+
addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
#ifdef CONFIG_LOGBUFFER
@@ -350,6 +357,7 @@
/* reserve TLB table */
addr -= (4096 * 4);
+
/* round down to next 64 kB limit */
addr &= ~(0x10000 - 1);
@@ -357,6 +365,7 @@
debug("TLB table at: %08lx\n", addr);
#endif
+
/* round down to next 4 kB limit */
addr &= ~(4096 - 1);
debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
@@ -378,6 +387,7 @@
addr -= gd->mon_len;
addr &= ~(4096 - 1);
+
debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
#ifndef CONFIG_SPL_BUILD
@@ -401,6 +411,7 @@
gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
#endif
+
addr_sp -= sizeof (gd_t);
id = (gd_t *) addr_sp;
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
@@ -422,6 +433,8 @@
addr_sp += 128; /* leave 32 words for abort-stack */
gd->irq_sp = addr_sp;
#endif
+
+
debug("New Stack Pointer is: %08lx\n", addr_sp);
@@ -437,13 +450,20 @@
gd->relocaddr = addr;
gd->start_addr_sp = addr_sp;
- gd->reloc_off = addr - _TEXT_BASE;
+ gd->reloc_off = addr - _TEXT_BASE;
+
debug("relocation Offset is: %08lx\n", gd->reloc_off);
+
memcpy(id, (void *)gd, sizeof(gd_t));
- relocate_code(addr_sp, id, addr);
+ GPMDAT_REG = 0x9;
+
+ //relocate_code(addr_sp, id, addr);
/* NOTREACHED - relocate_code() does not return */
+ void board_init_r(gd_t *id, ulong dest_addr);
+ board_init_r(id,addr);
}
#if !defined(CONFIG_SYS_NO_FLASH)
@@ -468,6 +488,8 @@
ulong flash_size;
#endif
+ GPMDAT_REG = 0x7;
+
gd = id;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
@@ -535,7 +557,7 @@
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts(failed);
- hang();
+ //hang();
}
#endif
@@ -648,6 +670,7 @@
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
+ puts("here");
main_loop();
}
最后打印的结果如下:
U-Boot 2012.07 (Sep 16 2012 - 22:46:00) for SMDK6410
CPU: S3C6410@533MHz
Fclk = 533MHz, Hclk = 133MHz, Pclk = 66MHz (ASYNC Mode)
Board: SMDK6410
DRAM: 128 MiB
WARNING: Caches not enabled
Flash: *** failed ***
NAND: No oob scheme defined for oobsize 218
2048 MiB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CS8900-0
Hit any key to stop autoboot: 0
SMDK6410 # print
Unknown command 'print' - try 'help'
可以看出u-boot的问题还很多,需要继续调试。