序列信号发生器

序列信号发生器，在clk信号作用下周期性输出“0010110111"

module seqgen( clk, rst_n, Q);
	input clk, rst_n;
	output Q;
    reg Q;
    reg [9:0] Q_temp;

    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            Q <= 1'b0;
            Q_temp <= 10'b0010110111;
        end
        else begin
            Q <= Q_temp[9];
            Q_temp <= {Q_temp[8:0],Q_temp[9]};
        end
    end
endmodule