利用硬件描述语言实现交通灯控制模型1，顶层连接

可以通过在程序设置时间点，实现白天和黑夜的模式切换

白天人行道交通灯是规律的绿黄红变化

黑夜是有人按键才会30秒后变为绿灯

顶层文件代码：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

 

ENTITY dingceng IS

PORT( clk : in std_LOGIC;

key1,key2,key3,key4,key5: IN STD_LOGIC;

seg7data: OUT STD_LOGIC_VECTOR(7 downto 0);

seg7com: OUT STD_LOGIC_VECTOR(3 downto 0)

);

END dingceng;

 

 

ARCHITECTURE example OF dingceng IS

 

component fenpin is

      port(clk:in std_logic; -----输入时钟

           clk_out1:out std_logic; -----输出1hzʱ

           clk_out2:out std_logic); ----输出100hzclk

end component;

 

component baitianheiyejishuqi is

         port (clk_out1:in std_logic;  ----输入1hz的时钟

               count_day:out std_logic ); -----输出一个状态 夜间为1  白天为0

end component;

 

 

component kongzhi2 is

          port(clk_out1:in std_logic;   ---输入1hz时钟

            enable: in std_logic;   ----使能端 1hz信号

           flag :out  std_logic;     ----中间信号

           count_day_0: buffer integer range 0 to 44 :=44);  

end component;

 

 

component kongzhi is

          port(on_off0:in std_logic;    ---按一下键

               flag:in std_logic;

            strobe: out std_logic;

               clk_out1:in std_logic;   ---输入1hz的时钟

            enable: buffer std_logic); ---使能端 输出持续45秒的1hz的时钟

end component;

 

 

component heiye is

     

       port (  NUM00,NUM10,NUM20,NUM30: buffer STD_LOGIC_VECTOR(3 DOWNTO 0);

               enable: in std_logic;

          strobe: in std_logic;

         count_day_0: in integer range 0 to 45;

               count_day:in std_logic );

end component;

 

 

 

component heiye2 is

        port ( NUM01,NUM11,NUM21,NUM31 : buffer STD_LOGIC_VECTOR(3 DOWNTO 0);

         strobe: in std_logic; --------与clk_out1组成使能端的电平状态 0 表示无按键  1 有

         clk_out2 : in std_logic;  ------100hz扫频

               count_day:in std_logic ); -----白天黑夜状态量

end component;

 

 

 

component baitian45 is

         port(clk_out1:in std_logic;   ---输入1hz时钟  

              count_day : in std_logic;

              count_day_0 : buffer integer range 0 to 44 := 44);   

end component;

 

 

component baitian is

         port ( NUM02,NUM12,NUM22,NUM32 : buffer STD_LOGIC_VECTOR(3 DOWNTO 0);

                clk_out1:in std_logic;

          count_day_0: in integer range 0 to 45;

                count_day:in std_logic );  

end component;

 

 

component jianpan is

             PORT(key5_out: out STD_LOGIC;

            key5: IN STD_LOGIC); ------5个按键

end component;

 

 

component xiaodou is

            port(on_off: in std_logic; ------输入信号 按键

                 clk: in std_logic; ------输入时钟信号

           clk_out2: in std_logic;---100hz的输入信号

           on_off0: out std_logic); -----消抖后的输出信号

end component;

 

 

component dongtaisaomiao is

          PORT ( CLK : IN STD_LOGIC;  -----输入100hz时钟 led1，2,3,4的数

              data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

              NUM0,NUM1,NUM2,NUM3 : inout STD_LOGIC_VECTOR(3 DOWNTO 0);-------四个显示管的数字  

           count_day:in std_logic;

             strobe: in std_logic;  

               enable: in std_logic;  

               xianshiguan : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

end component;

 

SIGNAL a:STD_LOGIC;

SIGNAL b:STD_LOGIC;

SIGNAL c:std_logic;

SIGNAL l:STD_LOGIC;

SIGNAL m:STD_LOGIC;

SIGNAL n:integer range 0 to 44:=44;

SIGNAL k:STD_LOGIC;

SIGNAL e:STD_LOGIC;

SIGNAL f:STD_LOGIC_VECTOR(3 downto 0);

SIGNAL g:STD_LOGIC_VECTOR(3 downto 0);

SIGNAL h:STD_LOGIC_VECTOR(3 downto 0);

SIGNAL i:STD_LOGIC_VECTOR(3 downto 0);

SIGNAL d:integer range 0 to 44:=44;

SIGNAL j:STD_LOGIC;

SIGNAL keysignal1:STD_LOGIC;

SIGNAL keysignal2:STD_LOGIC;

SIGNAL keysignal3:STD_LOGIC;

SIGNAL keysignal4:STD_LOGIC;

SIGNAL keysignal5:STD_LOGIC;

SIGNAL f1:STD_LOGIC_VECTOR(3 downto 0);

SIGNAL g1:STD_LOGIC_VECTOR(3 downto 0);

SIGNAL h1:STD_LOGIC_VECTOR(3 downto 0);

SIGNAL i1:STD_LOGIC_VECTOR(3 downto 0);

SIGNAL f2:STD_LOGIC_VECTOR(3 downto 0);

SIGNAL g2:STD_LOGIC_VECTOR(3 downto 0);

SIGNAL h2:STD_LOGIC_VECTOR(3 downto 0);

SIGNAL i2:STD_LOGIC_VECTOR(3 downto 0);

 

 

BEGIN

 

 

 

   

keysignal5 <= key1; --S2

u1: fenpin PORT MAP (clk, a,b);

 

u2: baitianheiyejishuqi PORT MAP (a,c);

 

u3: kongzhi2 PORT MAP (a,l,m,n);

 

u4: kongzhi PORT MAP (k,m,e,a,l);

 

u5: heiye PORT MAP (f,g,h,i,l,e,n,c);

 

u6: heiye2 PORT MAP (f1,g1,h1,i1,e,b,c);

 

u7: baitian45 PORT MAP (a,c,d);

 

u8: baitian PORT MAP (f2,g2,h2,i2,b,d,c);

 

u9: jianpan PORT MAP (j,keysignal5);

 

u10: xiaodou PORT MAP (j,clk,b,k);

 

u11: dongtaisaomiao PORT MAP (b,seg7data,f,g,h,i,c,e,l,seg7com);

 

end ARCHITECTURE example;

下面附上模块之间关系连接图