分频
模块说明:通过对分频系统的循环,达到将50mhz的时钟分开成1hz时钟和100hz时钟的目的
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(clk:in std_logic; -----输入时钟
clk_out1:out std_logic; -----输出1hzʱ
clk_out2:out std_logic); ----输出100hzclk
end entity fenpin;
architecture behav of fenpin is
signal count1:integer range 0 to 24999999; -----分频系数
signal count2:integer range 0 to 249999; ---------分频系数
signal clk_data1:std_logic; ----clk_data1信号
signal clk_data2:std_logic; -----clk_data2信号
begin
shuchushizhong:process(clk)
begin
if clk'event and clk='1' then
if count1=24999999 then ----count1循环
count1<=0; -----
clk_data1<=not clk_data1; ---取反
else count1<=count1+1; -----count1循环
end if;
end if;
end process shuchushizhong;
clk_out1<=clk_data1; -----局部变量代入全局变量
dongtaisaomiaoshizhong:process(clk)
begin
if clk'event and clk='1' then ----时钟上升沿
if count2=249999 then
count2<=0;
clk_data2<=not clk_data2;
else count2<=count2+1;
end if;
end if;
end process dongtaisaomiaoshizhong;