利用硬件描述语言实现交通灯控制模型8，键盘和控制

键盘

 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

 

ENTITY jianpan IS

PORT(key2_out: out STD_LOGIC;

Key2: IN STD_LOGIC); ------5个按键

END jianpan;

 

ARCHITECTURE behave OF jianpan IS

 

SIGNAL keysignal1 :STD_LOGIC;  -------- 五个信号

SIGNAL keysignal2 :STD_LOGIC;

SIGNAL keysignal3 :STD_LOGIC;

SIGNAL keysignal4 :STD_LOGIC;

SIGNAL keysignal5 :STD_LOGIC;

 

 

BEGIN

 

Keysignal2 <= key2;

 

Key2_out<=keysignal2;

END ARCHITECTURE behave;

 

 

 

 

 

 

 

 

控制

模块说明：当键盘检测到有电平的变化，1hz的时钟进行45秒计数后，随着flag的改变，strobe状态也改变，取消45秒之后的计数

 

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

 

entity kongzhi is             ---夜间控制

port(on_off0:in std_logic;    ---按一下键

      flag:in std_logic;

  strobe: buffer std_logic;

     clk_out1:in std_logic;   ---输入1hz的时钟

  enable: out std_logic); ---使能端 输出持续45秒的1hz的时钟

end kongzhi;

 

ARCHITECTURE rtl OF kongzhi IS

    ----信号高电平有效     与1hz通过与门产生enable 1hz时钟

signal count4: integer range 0 to 44:=44;    -------45秒计数                                  多余-----------------------------------

 

begin

 

process(on_off0,flag)  -----按键按下或者flga改变

begin

   if(on_off0'event and on_off0='1') then -----按键上升沿

strobe <= '1';                            -----strobe有效

 if(on_off0'event and on_off0='1') then

 strobe <= '1';

 else

 if(flag='1') then

 strobe <= '0';       -----45秒倒计时后flga改变 strobe无效

 end if;

   if(flag='0') then

   strobe <= '0';

   end if;

end if;

end if;

 

end process;

 

enable <= clk_out1 and strobe;  -----信号高电平有效     与1hz时钟信号通过与门产生enable 1hz时钟

 

 

end rtl;

 

 

控制2

模块说明：当按键按下，开始计数，当控制模块的输出端enable计数45次之后，flag改变，将flag的信号改变状态输入控制模块，控制计数的中断

 

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

 

entity kongzhi2 is

port(clk_out1:in std_logic;   ---输入1hz时钟

  enable: in std_logic;   ----使能端 1hz信号

  flag :out  std_logic;     ----中间信号

  count_day_0: buffer integer range 0 to 44 :=44);   

end kongzhi2;

 

 

ARCHITECTURE rtl OF kongzhi2 IS

signal flag1: std_logic;     ----中间信号

 

 

begin

P2: PROCESS(clk_out1)                                  

BEGIN

IF( enable'EVENT AND enable ='1' ) then --使能端1hz

    if count_day_0 = 0  then count_day_0 <= 44;

      flag1 <= not flag1;

 else count_day_0 <= count_day_0-1;

 end if;

 

 

END IF;

flag <= flag1;  ----变量带入到信号  输出flga

END PROCESS P2;

 

end rtl;

 

 

消除抖动

模块说明：通过变量的传递和运算，稳定输出一个高电平，

 

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

 

entity xiaodou is

port(on_off: in std_logic; ------输入信号 按键

        clk: in std_logic; ------输入时钟信号

  clk_out2: in std_logic;---100hz的输入信号

  on_off0: out std_logic); -----消抖后的输出信号

end xiaodou;

 

 

 ARCHITECTURE rtl OF xiaodou IS

 

 signal on_off_temp1 : std_logic; -----中间变量1

  signal on_off_temp2 : std_logic; ----中间变量2

   signal on_off_temp3 : std_logic;----中间变量3

begin

 

process(clk_out2)

begin

IF (clk_out2'lastvalue=’1’ AND clk_out2 ='0') ----消抖信号下降沿

then

on_off_temp1 <= not on_off; -----按键信号 代入变量1

     on_off_temp2 <= on_off_temp1; ------变量1代入变量2

end IF;

end process;

 

on_off_temp3 <= on_off_temp2; ---变量2代入变量3

 

process(clk)

begin

if(clk'EVENT AND clk='1') ------系统时钟上升沿

then

on_off0<=clk_out2 and on_off_temp1 and on_off_temp3; ------变量运算后 输出一个稳定的0.01秒的高电平

end if;

end process;

 

end rtl;