基于Verilog语言的13进制计数器设计

基于Verilog语言的13进制计数器设计

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/10 15:37:39
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//
module top(
    input clk,
    input rst,
    output reg[3:0] counter
    );
always @(posedge clk or posedge rst)
begin
    if(rst) 
    counter<=4'b0000;
    else 
    begin
    if(counter==4'b1100)
    counter<=4'b0000;
    else    
    counter<=counter+1;
    end
end 
endmodule

仿真文件

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/10 16:21:14
// Design Name: 
// Module Name: behave
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module behave;
reg clk,rst;//input
wire[3:0] counter;//output
top U1(.clk(clk),.rst(rst),.counter(counter));//module callback
    always  
         begin   
             #10 clk = ~clk;  
         end  
     initial  //==C reg 
         begin  
             clk = 1'b0;  
             rst = 1'b0;   
             #20 rst = 1'b1;  
             #10 rst = 1'b0;   
             #1000;   
         end  
endmodule