Qualcomm QUP源码详解

相关文件路径：

• standard_oem/tz_8155/trustzone_images/core/settings/buses/qup_accesscontrol/qupv3/config/855/QUPAC_Access.c
• standard_oem/tz_8155/trustzone_images/core/settings/buses/qup_accesscontrolqupv3/interface/QupACCommonIds.h

QUPAC_Access.c配置：

const QUPv3_se_security_permissions_type qupv3_perms_auto[] =
{
  /*   PeriphID,         ProtocolID,               Mode, NsOwner,bAllowFifo,bLoad,bModExcl  */
  { QUPV3_0_SE0, QUPV3_PROTOCOL_SPI,     QUPV3_MODE_GSI, AC_HLOS,       TRUE, TRUE, FALSE }, // VIP SPI MASTER / SLAVE
  /*QUPV3_0_SE1*/
  { QUPV3_0_SE2, QUPV3_PROTOCOL_I2C,     QUPV3_MODE_FIFO,AC_HLOS,      TRUE, TRUE,FALSE }, // HS-I2S
  /*QUPV3_0_SE3*/ 
  { QUPV3_0_SE4, QUPV3_PROTOCOL_I2C,     QUPV3_MODE_FIFO,AC_HLOS,      TRUE, TRUE,FALSE }, // AUX I2C
  /*QUPV3_0_SE5*/
  /*QUPV3_0_SE6*/
  { QUPV3_0_SE7, QUPV3_PROTOCOL_I2C,     QUPV3_MODE_FIFO,AC_HLOS,      TRUE, TRUE,FALSE }, // USB I2C
  /*QUPV3_1_SE0*/
  { QUPV3_1_SE1, QUPV3_PROTOCOL_UART_2W, QUPV3_MODE_GSI,  AC_HLOS,     FALSE,TRUE, FALSE}, // SIRFStar GNSS
  { QUPV3_1_SE2, QUPV3_PROTOCOL_I2C,     QUPV3_MODE_FIFO, AC_HLOS,     TRUE, TRUE,FALSE }, // SENSOR I2C
  /*QUPV3_1_SE3*/
  { QUPV3_1_SE4, QUPV3_PROTOCOL_UART_2W, QUPV3_MODE_FIFO,AC_HLOS,      TRUE,FALSE,FALSE }, // Debug
  /*QUPV3_1_SE5*/
  { QUPV3_2_SE0, QUPV3_PROTOCOL_UART_2W, QUPV3_MODE_FIFO,AC_HLOS,      TRUE, TRUE,FALSE }, // VIP UART (only Tx & Rx)
  /*QUPV3_2_SE1*/
  /*QUPV3_2_SE2*/  
  { QUPV3_2_SE3, QUPV3_PROTOCOL_UART_4W, QUPV3_MODE_FIFO,AC_HLOS,      TRUE, TRUE,FALSE }, // BT HCI
  /*QUPV3_2_SE4*/
  { QUPV3_2_SE5, QUPV3_PROTOCOL_I2C,     QUPV3_MODE_FIFO,AC_HLOS,      TRUE, TRUE,FALSE }, // DISPLAY I2C
};

QUPv3_se_security_permissions_type 定义：

/** QUPv3 serial engine configuration and permissions devcfg
    data structure */
typedef struct
{
  QUPV3_PERIPHID periph;        /* The SE peripheral to config and assign */
  QUPv3_protocol_type protocol; /* The protocol to use for this SE */
  QUPv3_mode_type mode;         /* The DMA/FIFO mode to use for this SE */
  uint32 uAC;                   /* Access control perms for this SE */
  boolean bAllowFifo;           /* Whether to allow FIFO mode for this SE */
  boolean bLoad;                /* Whether to load the firmware for this SE */
  boolean bModExclusive;        /* Whether TZ should have exclusive access when 
                                   a modify ownership operation has been 
                                   performed (TRUE), or whether only the GPIO
                                   ownership should be modified (FALSE) */
} QUPv3_se_security_permissions_type;

QUPV3_PERIPHID 定义：

/** QUPV3 serial engine IDs */
typedef enum {
   PERIPH_ENUM_MIN = 0,
   QUPV3_0_SE0 = PERIPH_ENUM_MIN,
   QUPV3_0_SE1,
   QUPV3_0_SE2,
   QUPV3_0_SE3,
   QUPV3_0_SE4,
   QUPV3_0_SE5,
   QUPV3_0_SE6,
   QUPV3_0_SE7,
   QUPV3_1_SE0,
   QUPV3_1_SE1,
   QUPV3_1_SE2,
   QUPV3_1_SE3,
   QUPV3_1_SE4,
   QUPV3_1_SE5,
   QUPV3_1_SE6,
   QUPV3_1_SE7,
   QUPV3_2_SE0,
   QUPV3_2_SE1,
   QUPV3_2_SE2,
   QUPV3_2_SE3,
   QUPV3_2_SE4,
   QUPV3_2_SE5,
   QUPV3_2_SE6,
   QUPV3_2_SE7,
   QUPV3_SSC_SE0,
   QUPV3_SSC_SE1,
   QUPV3_SSC_SE2,
   QUPV3_SSC_SE3,
   QUPV3_SSC_SE4,
   QUPV3_SSC_SE5,
   QUPV3_SSC_SE6,
   QUPV3_SSC_SE7,
   QUPV3_SE_END,
   QUPV3_GPII_START = QUPV3_SE_END,
   QUPV3_0_GPII0 = QUPV3_GPII_START,
   QUPV3_0_GPII1,
   QUPV3_0_GPII2,
   QUPV3_0_GPII3,
   QUPV3_0_GPII4,
   QUPV3_0_GPII5,
   QUPV3_0_GPII6,
   QUPV3_0_GPII7,
   QUPV3_0_GPII8,
   QUPV3_0_GPII9,
   QUPV3_0_GPII10,
   QUPV3_0_GPII11,
   QUPV3_0_GPII12,
   QUPV3_0_GPII13,
   QUPV3_0_GPII14,
   QUPV3_0_GPII15,
   QUPV3_1_GPII0,
   QUPV3_1_GPII1,
   QUPV3_1_GPII2,
   QUPV3_1_GPII3,
   QUPV3_1_GPII4,
   QUPV3_1_GPII5,
   QUPV3_1_GPII6,
   QUPV3_1_GPII7,
   QUPV3_1_GPII8,
   QUPV3_1_GPII9,
   QUPV3_1_GPII10,
   QUPV3_1_GPII11,
   QUPV3_1_GPII12,
   QUPV3_1_GPII13,
   QUPV3_1_GPII14,
   QUPV3_1_GPII15,
   QUPV3_2_GPII0,
   QUPV3_2_GPII1,
   QUPV3_2_GPII2,
   QUPV3_2_GPII3,
   QUPV3_2_GPII4,
   QUPV3_2_GPII5,
   QUPV3_2_GPII6,
   QUPV3_2_GPII7,
   QUPV3_2_GPII8,
   QUPV3_2_GPII9,
   QUPV3_2_GPII10,
   QUPV3_2_GPII11,
   QUPV3_2_GPII12,
   QUPV3_2_GPII13,
   QUPV3_2_GPII14,
   QUPV3_2_GPII15,
   QUPV3_SSC_GPII0,
   QUPV3_SSC_GPII1,
   QUPV3_SSC_GPII2,
   QUPV3_SSC_GPII3,
   QUPV3_SSC_GPII4,
   QUPV3_SSC_GPII5,
   QUPV3_SSC_GPII6,
   QUPV3_SSC_GPII7,
   QUPV3_SSC_GPII8,
   QUPV3_SSC_GPII9,
   QUPV3_SSC_GPII10,
   QUPV3_SSC_GPII11,
   QUPV3_SSC_GPII12,
   QUPV3_SSC_GPII13,
   QUPV3_SSC_GPII14,
   QUPV3_SSC_GPII15,
   PERIPH_MAX_ID
} QUPV3_PERIPHID;

QUPv3_protocol_type定义：

/** QUPv3 protocols */
typedef enum
{
  QUPV3_PROTOCOL_NONE = 0,
  QUPV3_PROTOCOL_SPI  = 1,
  QUPV3_PROTOCOL_UART = 2,
  QUPV3_PROTOCOL_UART_2W = QUPV3_PROTOCOL_UART,
  QUPV3_PROTOCOL_I2C  = 3,
  QUPV3_PROTOCOL_I3C  = 4,
  QUPV3_PROTOCOL_SPI_SLAVE  = 5,
  QUPV3_PROTOCOL_AFC        = 6,
  QUPV3_PROTOCOL_MAX,
  QUPV3_PROTOCOL_UART_4W = QUPV3_PROTOCOL_UART + 16,
  QUPV3_PROTOCOL_UINT32 = 0x7fffffff
} QUPv3_protocol_type;

QUPv3_mode_type定义：

/** QUPv3 FIFO/DMA access modes */
typedef enum
{
  QUPV3_MODE_FIFO = 0,
  QUPV3_MODE_CPU_DMA = 1,
  QUPV3_MODE_GSI = 2,
  QUPV3_MODE_MAX,
  QUPV3_MODE_UINT32 = 0x7fffffff
} QUPv3_mode_type;