the mapping between virtual addresses and physical addresses

a page table is the data structure used by a virtual memory computer operating system to store the mapping between virtual addressess and physical addresses.

the virtual addresses are used by accessing process and the physical address used by accessing hardware.

the page table is where the operating system storess its mappings of  virtual addresses to physical addresses. 

the translation process

the cpu's memory management uint (MMU).store a cache of recently used mapping from the operating system's page table.this is called the translation lookaside buffer(TLB).which is an associative cache.

when a virtual address need to be translated into a physical address the TLB is serched first.if a mach is found.(a TLB  hit)the physical address is returned and  memory access can continue.however, there is no mach(called a TLB miss).the handler will typically look up the address mapping in the page table to see whether the mapping exits(a page walk).if one exits,it is writen back ot the TBL.(this is must be done ,as the hardware accesses memory through the TLB in a virtual memory system).the fauting instrucation is restarted(this may happen in parallel as well).this subsequent translation will found a TLB hit.and the memory access will continue.