digital loopback mode

1、About the Digital Loopback Mode

In the digital loopback mode, the receive signals are connected internally through multiplexers to the corresponding transmit signals。This mode allows testing of serial port code with a single DSP device; the McBSP receives the data it transmits.

2、About the Clock Stop Mode

The clock stop mode supports the SPI master-slave protocol. If you will not be using the SPI protocol, you can clear CLKSTP to disable the clock stop mode.

In the clock stop mode, the clock stops at the end of each data transfer. At the beginning of each data transfer, the clock starts immediately (CLKSTP = 10b) or after a half-cycle delay (CLKSTP = 11b). The CLKXP bit determines whether the starting edge of the clock on the CLKX pin is rising or falling. The CLKRP bit determines  hether receive data is sampled on the rising or falling edge of the clock shown on the CLKR pin. 

Note that in the clock stop mode, the receive clock is tied internally to the transmit clock, and the receive frame-sync signal is tied internally to the transmit frame-sync signal.

转载于:https://www.cnblogs.com/elaron/archive/2011/07/26/2116907.html