- 博客(8)
- 资源 (16)
- 收藏
- 关注
RSS订阅原创 vi/vim 注释字体颜色的设置
在vi中被注释掉的字体颜色默认为蓝色，无法看清，通过设置用户根目录下.vimrc文件，可以更改颜色的配置。通过hi命令来修改注释的颜色，使用方法：设置关键字为蓝色非粗体 ：hi Identifier ctermfg =blue cterm=none （bold 就设置成粗体） 1、vi ~/.vimrc 加入如下内容：hi Comment ctermfg =blue
2015-08-28 13:53:14
11402
原创 systemverilog中阻塞和非阻塞事件以及同步
一、SV中非阻塞事件module test;event ev1, ev2;//belong to logic function partalways@(ev1) $display("ev1 triggered at %0ts", $time);initial wait(ev2.triggered)$display("ev2 triggered at %0ts
2015-08-14 10:07:19
3931
原创 systemverilog中$value$plusargs的用法
package pa;......endpackageprogram pr;import pa::*;......;initial begin......;void'($value$plusargs("s1 = %s", s));$display("s1 is %s=n", s);#1000;$exit();endendprogram
2015-08-14 09:46:23
5679
转载 Chapter 11 – Running the simulation
To run thesimulation, we simply execute the provided Makefile in the GitHub repository:$ make -f Makefile.vcsThe testbenchwill generate random inputs and then those inputs will be sent to the
2015-08-14 09:42:43
949
转载 Chapter 10 – Test
At last, we needto create one more block: the test. This block will derive from the uvm_test classand it will have two purposes:Create the env blockConnect the sequencer to the sequenceYou m
2015-08-14 09:40:54
497
转载 Chapter 8 – Scoreboard
The scoreboardis a crucial element in a self-checking environment, it verifies the properoperation of a design at a functional level. This component is the mostdifficult one to write, it varies from p
2015-08-14 09:37:09
773
转载 Chapter 7 – Agent
We have bothmonitors, the sequencer and the driver, so the next step is to connect them up.This is a job for the agent.An agent doesn’trequire a run phase, there is no simulation code to be executed
2015-08-14 09:22:27
641
转载 Chapter 6 – Monitor
The monitor is aself-contained model that observes the communication of the DUT with thetestbench. At most, it should observe the outputs of the design and, in case ofnot respecting the protocol’s rul
2015-08-04 16:22:15
804
2017年一建《水利水电工程管理与实务》教材电子版.pdf
2017-11-10
PCI_Express_Base_Specification_Revision_4.0
2017-11-10
UVM_1.1_Class_Reference_Final
2015-09-16
uvm-cookbook-sequences-guide-verification-academy
2015-09-16
coverage-cookbook-complete-verification-academy
2015-09-16
空空如也
TA创建的收藏夹 TA关注的收藏夹
TA关注的人