Fsm serialdata

题目：

See also: Serial receiver

Now that you have a finite state machine that can identify when bytes are correctly received in a serial bitstream, add a datapath that will output the correctly-received data byte. out_byte needs to be valid when done is 1, and is don't-care otherwise.

Note that the serial protocol sends the least significant bit first.

代码：

module top_module(

    input clk,

    input in,

    input reset,    // Synchronous reset

    output [7:0] out_byte,

    output done

); //

    parameter IDLE=0,START=1,DATA1=2,DATA2=3,DATA3=4,DATA4=5,DATA5=6,DATA6=7,DATA7=8,DATA8=9,STOP=10,ERROR=11;

    reg [3:0] state;

    reg [3:0] next_state;

    reg [7:0] out_reg;

   

    always @(posedge clk)begin

        if(reset)

            state <= IDLE;

           else

            state <= next_state;

    end

   

    always @(*)

        begin

            case(state)

                IDLE: next_state = in?IDLE:START;

                START:next_state = DATA1;

                DATA1:next_state = DATA2;

                DATA2:next_state = DATA3;

                DATA3:next_state = DATA4;

                DATA4:next_state = DATA5;

                DATA5:next_state = DATA6;

                DATA6:next_state = DATA7;

                DATA7:next_state = DATA8;

                DATA8:next_state = in?STOP:ERROR;

                ERROR:next_state = in?IDLE:ERROR;

                STOP :next_state = in?IDLE:START;

                default:next_state = IDLE;

            endcase

        end

               

       always @(posedge clk)begin

        if(reset)

            out_reg <= 8'd0;

        else

            case(next_state)

                DATA1:out_reg[0] <= in;

                DATA2:out_reg[1] <= in;

                DATA3:out_reg[2] <= in;

                DATA4:out_reg[3] <= in;

                DATA5:out_reg[4] <= in;

                DATA6:out_reg[5] <= in;

                DATA7:out_reg[6] <= in;

                DATA8:out_reg[7] <= in;

                default:out_reg <= out_reg;

            endcase

       end



    // Use FSM from Fsm_serial

    assign done = (state==STOP)?1:0;

    assign out_byte = (state==STOP)?out_reg:0;



    // New: Datapath to latch input bits.

               



Endmodule