HDLBits 答案之Fsm serialdata

最新推荐文章于 2023-02-18 21:52:54 发布

IC打工人

最新推荐文章于 2023-02-18 21:52:54 发布

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文章标签： fpga开发 verilog

本文链接：https://blog.csdn.net/weixin_43859941/article/details/123387149

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纯菜鸟，最傻瓜的办法写的...各位谨慎采纳。

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //

    parameter idle=10,s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7,s8=8,sp=9,fd=11;
    reg [3:0] state,nstate;
    reg m1,m2,m3,m4,m5,m6,m7,m8;
    always @(posedge clk) begin
        if(reset)
            state<=idle;
        else 
            state<=nstate;
    end
    
    always @(*) begin
        case(state)
            idle: nstate=!in?s0:idle;
            s0:   nstate=s1;
            s1:   nstate=s2;
            s2:   nstate=s3;            
            s3:   nstate=s4;            
            s4:   nstate=s5;            
            s5:   nstate=s6;            
            s6:   nstate=s7;
            s7:   nstate=s8;
            s8:   nstate=in?sp:fd;
            sp:   nstate=in?idle:s0;
            fd:   nstate=in?idle:fd;
            default: nstate=idle;
        endcase
    end
    
    always @(posedge clk)
        if(reset)
            m1<=0;
    else if (nstate==s1)
            m1<=in;
    else    
            m1<=m1;
    
     always @(posedge clk)
        if(reset)
            m2<=0;
    else if (nstate==s2)
            m2<=in;
    else    
            m2<=m2;
    
        always @(posedge clk)
        if(reset)
            m3<=0;
    else if (nstate==s3)
            m3<=in;
    else    
            m3<=m3;
    
        always @(posedge clk)
        if(reset)
            m4<=0;
    else if (nstate==s4)
            m4<=in;
    else    
            m4<=m4;
    
        always @(posedge clk)
        if(reset)
            m5<=0;
    else if (nstate==s5)
            m5<=in;
    else    
            m5<=m5;
    
        always @(posedge clk)
        if(reset)
            m6<=0;
    else if (nstate==s6)
            m6<=in;
    else    
            m6<=m6;
    
        always @(posedge clk)
        if(reset)
            m7<=0;
    else if (nstate==s7)
            m7<=in;
    else    
            m7<=m7;
    
        always @(posedge clk)
        if(reset)
            m8<=0;
    else if (nstate==s8)
            m8<=in;
    else    
            m8<=m8;
    
   
    assign done=(state==sp);
    assign out_byte=(state==sp)?{m8,m7,m6,m5,m4,m3,m2,m1}:0;