Fsm serialdp

题目：

See also: Serial receiver and datapath

We want to add parity checking to the serial receiver. Parity checking adds one extra bit after each data byte. We will use odd parity, where the number of 1s in the 9 bits received must be odd. For example, 101001011 satisfies odd parity (there are 5 1s), but 001001011 does not.

Change your FSM and datapath to perform odd parity checking. Assert the done signal only if a byte is correctly received and its parity check passes. Like the serial receiver FSM, this FSM needs to identify the start bit, wait for all 9 (data and parity) bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.

You are provided with the following module that can be used to calculate the parity of the input stream (It's a TFF with reset). The intended use is that it should be given the input bit stream, and reset at appropriate times so it counts the number of 1 bits in each byte.

module parity (
    input clk,
    input reset,
    input in,
    output reg odd);

    always @(posedge clk)
        if (reset) odd <= 0;
        else if (in) odd <= ~odd;

endmodule

Note that the serial protocol sends the least significant bit first, and the parity bit after the 8 data bits.

代码：

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
    parameter IDLE=0,START=1,DATA1=2,DATA2=3,DATA3=4,DATA4=5,DATA5=6,DATA6=7,DATA7=8,DATA8=9,STOP=10,ERROR=11,ODD=12;
    reg [3:0] state;
    reg [3:0] next_state;
    reg [7:0] out_reg;
    reg odd;
    
    always @(posedge clk)begin
        if(reset)
            state <= IDLE;
        else
            state <= next_state;
    end
    
    always @(*)
        begin
            case(state)
                IDLE: next_state = in?IDLE:START;
                START:next_state = DATA1;
                DATA1:next_state = DATA2;
                DATA2:next_state = DATA3;
                DATA3:next_state = DATA4;
                DATA4:next_state = DATA5;
                DATA5:next_state = DATA6;
                DATA6:next_state = DATA7;
                DATA7:next_state = DATA8;
                DATA8:next_state = ODD;
                ODD  :next_state = in?STOP:ERROR;
                ERROR:next_state = in?IDLE:ERROR;
                STOP :next_state = in?IDLE:START;
                default:next_state = IDLE;
            endcase
        end
                
    always @(posedge clk)begin
        if(reset)
            out_reg <= 8'd0;
        else
            case(next_state)
                DATA1:out_reg[0] <= in;
                DATA2:out_reg[1] <= in;
                DATA3:out_reg[2] <= in;
                DATA4:out_reg[3] <= in;
                DATA5:out_reg[4] <= in;
                DATA6:out_reg[5] <= in;
                DATA7:out_reg[6] <= in;
                DATA8:out_reg[7] <= in;
                default:out_reg <= out_reg;
            endcase
    end
    


    // Use FSM from Fsm_serial
    assign done = ((state==STOP)&&(~odd))?1:0;
    assign out_byte = ((state==STOP)&&(~odd))?out_reg:0;

    // New: Datapath to latch input bits.
    always @(posedge clk)
        begin
            if(state==IDLE)
                sign <= 1;
            else
                sign <= 0;
        end
    parity u1(
        .clk(clk),
        .reset(reset || next_state == IDLE || next_state == START),
        .in(in),
        .odd(odd)
    );            

    // Modify FSM and datapath from Fsm_serialdata

    // New: Add parity checking.

endmodule