Fsm hdlc

题目：

​​​​​​​Synchronous HDLC framing involves decoding a continuous bit stream of data to look for bit patterns that indicate the beginning and end of frames (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a "flag" that indicate frame boundaries. To avoid the data stream from accidentally containing "flags", the sender inserts a zero after every 5 consecutive 1s which the receiver must detect and discard. We also need to signal an error if there are 7 or more consecutive 1s.

Create a finite state machine to recognize these three sequences:

• 0111110: Signal a bit needs to be discarded (disc).
• 01111110: Flag the beginning/end of a frame (flag).
• 01111111...: Error (7 or more 1s) (err).

When the FSM is reset, it should be in a state that behaves as though the previous input were 0.

Here are some example sequences that illustrate the desired operation.

代码：

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    parameter START=1,data1=2,data2=3,data3=4,data4=5,data5=6,DISC=7,FLAG=8,ERR=9,data6=10;
    reg [4:0] state;
    reg [4:0] next_state;
    
    always @(posedge clk)begin
        if(reset)
            state <= START;
        else
            state <= next_state;
    end
    
    always @(*)
        begin
            case(state)
                START: next_state = in?data1:START;
                data1: next_state = in?data2:START;
                data2: next_state = in?data3:START;
                data3: next_state = in?data4:START;
                data4: next_state = in?data5:START;
                data5: next_state = in?data6:DISC;
                data6: next_state = in?ERR:FLAG;
                DISC : next_state = in?data1:START;
                FLAG : next_state = in?data1:START;
                ERR  : next_state = in?ERR:START;
                default: next_state = START;
            endcase
        end
    
    assign disc = (state==DISC);
    assign flag = (state==FLAG);
    assign err  = (state==ERR);

endmodule