SPI drive

最新推荐文章于 2024-07-09 15:37:52 发布

bbbman7

最新推荐文章于 2024-07-09 15:37:52 发布

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文章标签： fpga开发

本文链接：https://blog.csdn.net/bbbman7/article/details/126708460

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module spi_drive
(
    //系统接口
 input sys_clk,
 input sys_rst_n,
   //用户接口
 input send_start,
 input [7:0] data_send,
 output reg send_done,
 //output [7:0] data_rec,

 //物理接口
 output reg spi_mosi,
 output reg spi_sclk,
 input spi_miso,
 output reg spi_cs
);

reg [1:0] clk_cnt,
reg [3:0] send_bit_cnt;
//reg [3:0] rec_bit_cnt;

wire pos_clk;
wire neg_clk;

//4分频得到上升沿和下降沿
always@(posedge sys_clk or negedge sys_rst_n)
begin
  if(~sys_rst_n)
   clk_cnt<=2'd0;
  else
   clk_cnt<=cnt_4+1'd1; 
end

//得到时钟的上升沿和下降沿
always@(posedge sys_clk or negedge sys_rst_n)
 begin
  if(!sys_rst_n)
   spi_sclk<=0;
  else if(spi_cs)
    spi_sclk<=0;
  else if(clk_cnt==2'd0)
     spi_sclk<=0;
  else if(clk_cnt==2'd2)
     spi_sclk<=1;
  else spi_sclk<=spi_sclk;
 end

//片选信号生成
always@(posedge sys_clk or negedge sys_rst_n)
begin
 if(!sys_rst_n)
  spi_cs<=1;
 else if(send_start)
  spi_cs<=0;
 else if(send_bit_cnt==4'd7&&clk_cnt==2'd3)
  spi_cs<=1;
 else 
  spi_cs<=spi_cs;
end


//发送位生成
always@(posedge sys_clk or negedge sys_rst_n)
begin
 if(!sys_rst_n)
  send_bit_cnt<=4'd0;
 else if(spi_cs)
  send_bit_cnt<=4'd0;
 else if(clk_cnt==2'd0)
  send_bit_cnt<=send_bit_cnt+1'd1;
 else 
  send_bit_cnt<=send_bit_cnt;
end

//发送数据
always@(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n)
  spi_mosi<=1'd0;
  else if(spi_cs)
   spi_mosi<=1'd0;
  else if(clk_cnt==2'd0)
   spi_mosi<=data_send[7-send_bit_cnt]
  else 
   spi_mosi<=spi_mosi;
end

//发送完成信号
always@(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n)
    send_done<=0;
  else if(send_bit_cnt==7&&clk_cnt==2'd3)
    send_done<=1;
  else 
    send_done<=1;
end
endmodule

module tb_spi_drive();

spi_drive u_spi_drive(
.sys_clk            (sys_clk)      ,
.sys_rst_n          (sys_rst_n)    ,
.send_start         (send_start),
.data_send          (data_send),
.send_done          (send_done),
.spi_mosi           (spi_mosi),
.spi_sclk           (spi_sclk),
.spi_miso           (spi_miso),
.spi_cs             (spi_cs)
);

 reg                   sys_clk   ;
 reg                   sys_rst_n ;
 reg                   send_start;
 reg [7:0]             data_send ;
 wire                  send_done ;
 wire                  spi_mosi  ;
 wire                  spi_sclk  ;
 //                   spi_miso  ;
 wire                   spi_cs   ; 

initial
begin
  sys_clk<=0;
  sys_rst_n<=0;
  #200
  sys_rst_n<=1;
  #100
  send_start<=1;
  data_send<=8'h55;
  #100
  send_start<=0;
end

always #10 sys_clk <= ~sys_clk； 
endmodule