按键消抖VERILOG

module top_module(
    input clk,
    input reset,
    input [3:0] key_in, //按键输入
    output [3:0] key_signal, //按键扫描
    output [7:0] led
);
    wire key;//4个按键输入相与来判断是否有按键被按下
    assign key=&key_in;
    reg [3:0] key_value;//存入按键判断值，判断按下还是释放
    wire push1,push2;
    always@(posedge clk)
        begin
            if(!reset)
                key_value<4'b1;
            else key_value<={key_value[2:0],key};           
        end
    assign wire push1=key_value[2]&&~key_value[1];
    assign wire push1=~key_value[2]&&key_value[0];
    
    //出现按键时进行20ms延时
    reg [19:0] cnt;
    always@(posedge clk)
        begin
            if(!reset)
                cnt<=19'b0;
            eles if(push1||push2)
                cnt<=19'b0;
            else if(cnt<999999)
                cnt<=cnt+1'b1;
            else cnt<=19‘b0                  
        end

                
   //按键扫描
     always@(posedge clk)
         begin
             if(!reset)
                 begin
                     key_signal<=4'b1; 
                 end
             else if(cnt=999999)
                 begin
                     key_signal<=key_in;
                 end
             else key_signal<4'b1;
         end
            //led控制
            always@(posedge clk)
                begin
                    if(reset) led<=8'hff;
                    else if (!key_signal[0]) led[0]<=~led[0];
                    else if (!key_signal[1]) led[1]<=~led[1];
                    else if (!key_signal[2]) led[2]<=~led[2];
                    else if (!key_signal[3]) led[3]<=~led[3];
                    else ;
                end
endmodule