Wince系统时钟配置

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于 2015-01-31 16:32:27 发布

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Wince系统时钟配置

此文档主要是基于wince和SMDK2416的BSP包对系统的时钟分配做一说明；

配置时钟代码的实现路径在在SMDK2450\SRC\INC\S3c2450.inc中；

;========================================================================

; PLL Value setting

; EBOOT and Kernel refers this value.

;=====================================================================================

; Fin =12MHz,

;

; MPLLout =(2m x Fin)/(p x 2**s), m=MDIV+8, p=PDIV, s=SDIV, Fin=10~30MHz

; (17,1,1)=300Mhz,(92,3,1)=400Mhz, (67,2,1)=450Mhz, (81,2,1)=534Mhz,

; (17,1,0)=600Mhz,(92,3,0)=800Mhz

;

; EPLLout =(m x Fin)/(p x 2**s), m=MDIV+8, p=PDIV+2, s=SDIV, Fin=10~100MHz

; (28,1,2)=36Mhz,(40,1,2)=48Mhz, (22,1,1)=60Mhz, (28,1,1)=72Mhz, (34,1,1)=84Mhz

; (40,1,1)=96Mhz

;=====================================================================================

上述说明为该文件选择不同的参数下的系统时钟；通过如下配置选择时钟频率；

[ BSP_TYPE= BSP_SMDK2450

;CLKVAL SETA 533

CLKVAL SETA 400133

;CLKVAL SETA 266

;CLKVAL SETA 400

;CLKVAL SETA 36

[ BSP_TYPE = BSP_SMDK2450

[ CLKVAL = 36

DVSON SETA 0

HCLKVAL SETA 18

Startup_MPLL EQU 36000000

Startup_Mdiv EQU 24

Startup_Pdiv EQU 4

Startup_Sdiv EQU 1

Startup_ARMCLKdiv EQU 0 ; 0 : ARMCLK = MPLL/1

; 1 : ARMCLK = MPLL/2

; 2 : ARMCLK = MPLL/3

; 3 : ARMCLK = MPLL/4

; 5 : ARMCLK = MPLL/6

; 7 : ARMCLK = MPLL/8

; 13 : ARMCLK = MPLL/12

; 15 : ARMCLK = MPLL/16

Startup_PREdiv EQU 0 ; 0x0 : PREDIV_CLK = MPLL

; 0x1 : PREDIV_CLK = MPLL/2

; 0x2 : PREDIV_CLK = MPLL/3

; 0x3 : PREDIV_CLK = MPLL/4

Startup_HALFHCLKdiv EQU 1 ; 0 :HCLKx1_2(SSMC) = HCLK

; 1 :HCLKx1_2(SSMC) = HCLK/2

Startup_PCLKdiv EQU 0 ; 0 : PCLK =HCLK

; 1 : PCLK =HCLK/2

Startup_HCLKdiv EQU 1 ; 0x0 : HCLK = PREDIV_CLK

; 0x1 : HCLK = PREDIV_CLK/2

; 0x3 : HCLK = PREDIV_CLK/4

]

[ CLKVAL = 400133 ;800

DVSON SETA 0

HCLKVAL SETA 133

Startup_MPLL EQU 800000000

Startup_Mdiv EQU 400

Startup_Pdiv EQU 3

Startup_Sdiv EQU 1

Startup_ARMCLKdiv EQU 1 ; 0 : ARMCLK = MPLL/1

; 1 : ARMCLK = MPLL/2

; 2 : ARMCLK = MPLL/3

; 3 : ARMCLK = MPLL/4

; 5 : ARMCLK = MPLL/6

; 7 : ARMCLK = MPLL/8

; 13 : ARMCLK = MPLL/12

; 15 : ARMCLK = MPLL/16

Startup_PREdiv EQU 2 ; 0 : PREDIV_CLK = MPLL

; 1 : PREDIV_CLK = MPLL/2

; 2 : PREDIV_CLK = MPLL/3

; 3 : PREDIV_CLK = MPLL/4

; PREdiv HCLKdiv

Startup_HCLKdiv EQU 1 ; 0 : HCLK =PREDIV_CLK

; 0x1 : HCLK = PREDIV_CLK/2

; 0x3 : HCLK = PREDIV_CLK/4

Startup_PCLKdiv EQU 1 ; 0 : PCLK =HCLK

; 1 : PCLK =HCLK/2

]

[ CLKVAL = 400 ;400/100

DVSON SETA 0

HCLKVAL SETA 100

Startup_MPLL EQU 800000000

Startup_Mdiv EQU 400

Startup_Pdiv EQU 3

Startup_Sdiv EQU 1

Startup_ARMCLKdiv EQU 1 ; 0 : ARMCLK = MPLL/1

; 1 : ARMCLK = MPLL/2

; 2 : ARMCLK = MPLL/3

; 3 : ARMCLK = MPLL/4

; 5 : ARMCLK = MPLL/6

; 7 : ARMCLK = MPLL/8

; 13 : ARMCLK = MPLL/12

; 15 : ARMCLK = MPLL/16

Startup_PREdiv EQU 3 ; 0 : PREDIV_CLK = MPLL

; 1 : PREDIV_CLK = MPLL/2

; 2 : PREDIV_CLK = MPLL/3

; 3 : PREDIV_CLK = MPLL/4

; PREdiv HCLKdiv

Startup_HCLKdiv EQU 1 ; 0 : HCLK =PREDIV_CLK

; 0x1 : HCLK = PREDIV_CLK/2

; 0x3 : HCLK = PREDIV_CLK/4

Startup_PCLKdiv EQU 1 ; 0 : PCLK =HCLK

; 1 : PCLK =HCLK/2

]

[ CLKVAL = 266 ;266/133

DVSON SETA 0

HCLKVAL SETA 133

Startup_MPLL EQU 533000000

Startup_Mdiv EQU 355

Startup_Pdiv EQU 4

Startup_Sdiv EQU 1

Startup_ARMCLKdiv EQU 1 ; 0 : ARMCLK = MPLL/1

; 1 : ARMCLK = MPLL/2

; 2 : ARMCLK = MPLL/3

; 3 : ARMCLK = MPLL/4

; 5 : ARMCLK = MPLL/6

; 7 : ARMCLK = MPLL/8

; 13 : ARMCLK = MPLL/12

; 15 : ARMCLK = MPLL/16

Startup_PREdiv EQU 1 ; 0 : PREDIV_CLK = MPLL

; 1 : PREDIV_CLK = MPLL/2

; 2 : PREDIV_CLK = MPLL/3

; 3 : PREDIV_CLK = MPLL/4

; PREdiv HCLKdiv

Startup_HCLKdiv EQU 1 ; 0 : HCLK =PREDIV_CLK

; 0x1 : HCLK = PREDIV_CLK/2

; 0x3 : HCLK = PREDIV_CLK/4

Startup_PCLKdiv EQU 1 ; 0 : PCLK =HCLK

; 1 : PCLK =HCLK/2

]

[ CLKVAL = 533

DVSON SETA 0

HCLKVAL SETA 133

Startup_MPLL EQU 533000000

Startup_Mdiv EQU 355

Startup_Pdiv EQU 4

Startup_Sdiv EQU 1

Startup_ARMCLKdiv EQU 0 ; 0 : ARMCLK = MPLL/1

; 8 : ARMCLK = MPLL/2

; 2 : ARMCLK = MPLL/3

; 9 : ARMCLK = MPLL/4

; 10 : ARMCLK = MPLL/6

; 11 : ARMCLK = MPLL/8

; 13 : ARMCLK = MPLL/12

; 15 : ARMCLK = MPLL/16

Startup_PREdiv EQU 0x1 ; 0x0 : PREDIV_CLK = MPLL

; 0x1 : PREDIV_CLK = MPLL/2

; 0x2 : PREDIV_CLK = MPLL/3

; 0x3 : PREDIV_CLK = MPLL/4

Startup_HCLKdiv EQU 0x1 ; 0x0 : HCLK = PREDIV_CLK

; 0x1 : HCLK = PREDIV_CLK/2

; 0x3 : HCLK = PREDIV_CLK/4

Startup_PCLKdiv EQU 1 ; 0 : PCLK =HCLK

; 1 : PCLK =HCLK/2

]

Startup_EMdiv EQU 32 ;EPLL -> 96Mhz

Startup_EPdiv EQU 1

Startup_ESdiv EQU 2

]

为保证核心板正常工作，需要对ARMCLK进行配置；为保证接下来的UART能使用，我们选择开启PCLK，至于其他相关外设，需要用到时再开启。
与时钟相关的寄存器有：LOCK(计数稳定时间)、CON0(分频寄存器)、DIV(分频)、CON（Fin的倍频）、SRC(控制时钟总的来源)
为保证正确的频率，强烈建议时钟设置顺序为：LOCK、DIV、CON、SRC；

对于各个时钟的使用说明芯片手册里做了如下描述；

The ARMCLK is used for ARM926EJcore, the main CPU of S3C2416. The HCLK is the reference clock forinternal AHBbus and peripherals such as the memory controller, the interrupt controller,LCD controller, the DMA,USB host block, System Controller, Power downcontroller and etc. The PCLK is used for internal APB bus andperipherals suchas WDT, IIS, I2C, PWM timer, ADC, UART, GPIO, RTC and SPI etc. DDRCLK is thedata strobeclock for mDDR/DDR2 memories. CAMclk is used for camera interfaceblock. HCLKCON and PCLKCON registersare used for clock gating of HCLK, PCLKrespectively. SCLKCON register is responsible for EPLLclk clock gatingonrelated modules.

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Wince系统时钟配置

Wince系统时钟配置此文档主要是基于wince和SMDK2416的BSP包对系统的时钟分配做一说明；配置时钟代码的实现路径在在SMDK2450\SRC\INC\S3c2450.inc中； ;========================================================================; PLL Value setting
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