The HLS tipping point （引爆点，转折点？）

Jason Cong

University of California, Los Angeles

Wolfgang Rosenstiel

Eberhard Karls Universita¨ t Tu¨bingen

 

The Tipping Point, by Malcolm Gladwell, defines the tipping point as ‘‘that magic moment when an idea, trend, or social behavior crosses a threshold, tips, and spreads like wildfire.’’ Given the initial success of third-generation high-level-synthesis (HLS) tools, one may wonder if and when such a tipping point will be reached. We see several forces accelerating the acceptance of HLS.

 

One force stems from（源于） the need to rapidly explore the large design spaces associated with modern SoC designs. The increasing complexity of algorithms and tight time-to-market requirements make it ever more difficult for designers to evaluate all possible options with manual RTL designs. HLS integrates different optimization approaches difficult for even an experienced designer to match, given constraints on latency, performance, and chip area. For example, it is very time-consuming to implement an adaptation of memory interfaces for transformations, like loop unrolling manually and efficiently at the register transfer level. An exploration of diverse solutions is only possible with automated HLS. The recent article, “Automated Path Finding Tool Chain for 3D-Stacked Integrated Circuits: Practical Case Study’’ by IMEC and Qualcomm is a good example (by Milojevicetal, to be published in the proceedings of the IEEE International Conference on 3D System Integration in September 2009).

 

Another emerging force is the result of an increased emphasis by the designers on power optimization. Techniques for low-power design can be applied at various levels in the design process, but have the largest impact at the behavior level. Although HLS for power optimization has been studied for more than a decade in academia, it was very difficult (if not impossible) to pass various power optimization decisions made during HLS to downstream RTL implementation tools. The recent introduction of standard interfaces for low-power design, such as UPF and CPF, now allow the HLS tools to output implementation-related power information along with RTL to guide logical and physical synthesis tools in aggressive power optimization. Some recent HLS tools implement techniques, such as clock gating, power gating, and multiple supply voltage control, together with RTL generation. This would be highly tedious if implemented manually.

 

Interconnect performance limitations can also be most effectively addressed at the behavior level. For example, the UCLA study in the April 2004 IEEE Transactions on Computer-Aided Design (pp. 550[1]564) pointed out that not all long wires are equally ‘‘harmful’’; only those crossed in a single clock cycle limit the clock frequency. This study proposed an HLS synthesis approach, coupled with global placement, which explicitly schedules multicycle communication on each long wire. Routability of an RTL design is another metric difficult to quantify and optimize, but RTL routing can also be optimized with behavior-level physical synthesis. Therefore, one can fully expect that the quality of HLS results, coupled with behavior-level physical synthesis, can exceed that of manual RTL design, because HLS optimizes in a much larger solution space.

 

FINALLY, HLS LEADS TO an early and integrated verification and validation of design. Given these trends and driving forces, we feel that we are getting close to the tipping point for the wide adoption of HLS.（但愿如此）

 

Jason Cong is Chancellor’s Professor at the University of California, Los Angeles.

Wolfgang Rosenstiel is a professor of computer engineering at Eberhard Karls Universita¨ t Tu¨bingen.