PCI设备与PCI桥的配置空间

置顶 chenxh..

已于 2023-06-16 17:23:38 修改

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分类专栏： PCIE学习文章标签：其他

于 2022-08-02 15:21:42 首次发布

本文链接：https://blog.csdn.net/chen_xing_hai/article/details/126102655

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PCI配置空间

HOST主桥通过配置读写事务报文访问设备的配置空间，PCI总线规定了三种类型的PCI配置空间。配置空间中出现的地址都是PCI总线域的地址。

(1)Agent设备配置空间(HeaderType.HeaderLayout=0)

(2)Bridge桥配置空间(HeaderType.HeaderLayout=1)

(3)Cardbus桥片配置空间(HeaderType.HeaderLayout=1)

电气特性决定了一个PCI总线上挂接的负载有限，如PCIe一个总线上只能接两个设备，需要接多个PCI设备时就需要使用PCI桥扩展出更多的PCI总线，一颗PCI设备树中最多256个设备(包括PCI桥)。

PCI桥的配置空间在系统软件遍历PCI总线树时配置，系统软件不需要专门的驱动程序配置PCI桥的使用方法，所以PCI桥也称透明桥。但也存在不透明桥，用于连接两个不同的处理器系统。PCI桥跨接在两个PCI总线间，下图使用PCI桥扩展PCI总线：

Primary Bus：上游总线，距离HOST主桥近的一端的总线；

Secondary Bus：下游总线，距离HOST主桥远的一端的总线；

PCI桥连接的总线属于同一个总线域，同一个总线域通过PCI桥进行数据交互时不需要进行地址转换。如x域内部总线通信不需要进行地址转换，而x域与y域进行通信时需要进行地址转换。设备22域设备21通信时只会占用PCI总线2的带宽，并不影响PCI总线0/1/3，这也是引入PCI桥的重要原因。

PCI桥不能扩展总线域，如在一个32位的PCI总线域中，所有设备共享4GB地址空间。

PCIE CapID表

PCI通用能力ID
/* Capability lists */

#define PCI_CAP_LIST_ID		0	/* Capability ID */
#define  PCI_CAP_ID_PM		0x01	/* Power Management */
#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
#define  PCI_CAP_ID_PCIX	0x07	/* PCI-X */
#define  PCI_CAP_ID_HT		0x08	/* HyperTransport */
#define  PCI_CAP_ID_VNDR	0x09	/* Vendor-Specific */
#define  PCI_CAP_ID_DBG		0x0A	/* Debug port */
#define  PCI_CAP_ID_CCRC	0x0B	/* CompactPCI Central Resource Control */
#define  PCI_CAP_ID_SHPC	0x0C	/* PCI Standard Hot-Plug Controller */
#define  PCI_CAP_ID_SSVID	0x0D	/* Bridge subsystem vendor/device ID */
#define  PCI_CAP_ID_AGP3	0x0E	/* AGP Target PCI-PCI bridge */
#define  PCI_CAP_ID_SECDEV	0x0F	/* Secure Device */
#define  PCI_CAP_ID_EXP		0x10	/* PCI Express */
#define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
#define  PCI_CAP_ID_SATA	0x12	/* SATA Data/Index Conf. */
#define  PCI_CAP_ID_AF		0x13	/* PCI Advanced Features */
#define  PCI_CAP_ID_EA		0x14	/* PCI Enhanced Allocation */
#define  PCI_CAP_ID_MAX		PCI_CAP_ID_EA
#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
#define PCI_CAP_SIZEOF		4

PCIE扩展能力ID
/* Extended Capabilities (PCI-X 2.0 and Express) */
#define PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)
#define PCI_EXT_CAP_VER(header)		((header >> 16) & 0xf)
#define PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)

#define PCI_EXT_CAP_ID_ERR	0x01	/* Advanced Error Reporting */
#define PCI_EXT_CAP_ID_VC	0x02	/* Virtual Channel Capability */
#define PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial Number */
#define PCI_EXT_CAP_ID_PWR	0x04	/* Power Budgeting */
#define PCI_EXT_CAP_ID_RCLD	0x05	/* Root Complex Link Declaration */
#define PCI_EXT_CAP_ID_RCILC	0x06	/* Root Complex Internal Link Control */
#define PCI_EXT_CAP_ID_RCEC	0x07	/* Root Complex Event Collector */
#define PCI_EXT_CAP_ID_MFVC	0x08	/* Multi-Function VC Capability */
#define PCI_EXT_CAP_ID_VC9	0x09	/* same as _VC */
#define PCI_EXT_CAP_ID_RCRB	0x0A	/* Root Complex RB? */
#define PCI_EXT_CAP_ID_VNDR	0x0B	/* Vendor-Specific */
#define PCI_EXT_CAP_ID_CAC	0x0C	/* Config Access - obsolete */
#define PCI_EXT_CAP_ID_ACS	0x0D	/* Access Control Services */
#define PCI_EXT_CAP_ID_ARI	0x0E	/* Alternate Routing ID */
#define PCI_EXT_CAP_ID_ATS	0x0F	/* Address Translation Services */
#define PCI_EXT_CAP_ID_SRIOV	0x10	/* Single Root I/O Virtualization */
#define PCI_EXT_CAP_ID_MRIOV	0x11	/* Multi Root I/O Virtualization */
#define PCI_EXT_CAP_ID_MCAST	0x12	/* Multicast */
#define PCI_EXT_CAP_ID_PRI	0x13	/* Page Request Interface */
#define PCI_EXT_CAP_ID_AMD_XXX	0x14	/* Reserved for AMD */
#define PCI_EXT_CAP_ID_REBAR	0x15	/* Resizable BAR */
#define PCI_EXT_CAP_ID_DPA	0x16	/* Dynamic Power Allocation */
#define PCI_EXT_CAP_ID_TPH	0x17	/* TPH Requester */
#define PCI_EXT_CAP_ID_LTR	0x18	/* Latency Tolerance Reporting */
#define PCI_EXT_CAP_ID_SECPCI	0x19	/* Secondary PCIe Capability */
#define PCI_EXT_CAP_ID_PMUX	0x1A	/* Protocol Multiplexing */
#define PCI_EXT_CAP_ID_PASID	0x1B	/* Process Address Space ID */
#define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */
#define PCI_EXT_CAP_ID_L1SS	0x1E	/* L1 PM Substates */
#define PCI_EXT_CAP_ID_PTM	0x1F	/* Precision Time Measurement */
#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PTM

PCI Agent 设备配置空间

参考 PCI Express Base Specification (kdocs.cn) 7.5.1.1 Type 0/1 Common Configuration Space、7.5.1.2 Type 0 Configuration Space Header

PCI设备一般会有默认配置信息(EEPROM或与程序放一起)，上电时由硬件完成配置空间的初始化。在未完成初始化之前，可以使用PCI总线规范规定的“Retry”周期使HOST主桥在合适的时机重新发起配置读写请求。

系统软件在使用CONFIG_ADDR和CONFIG_DATA寄存器完成配置空间的读写请求，根据设备配置空间初始化

PCI Agent (Type0)配置空间寄存器定义如下：

此处仅介绍软件感兴趣的寄存器

Vendor ID：0x00，只读，代码生产该PCI设备的厂商，为0xffff时表示无效

Device ID：0x02，只读，代表这个厂商生产的具体设备；

Revision ID：0x08，只读，记载PCI设备版本号，可作为Device ID的扩展；

Class Code：0x09，读写，记载PCI设备类型，可供系统软件识别当前PCI设备类型从而做不同处理，该字段由三个字段组成：

Base Class Code ：将设备分类为显卡、网卡、PCI桥等设备；

Sub Class Code：对这些设备进行进一步分类；

Interface：定义编程接口。

Header Type：0x0e，只读，系统软件需要根据此寄存器知道配置空间类型，由8位组成：

bit7：1-多功能设备，0-单功能设备

bit6-0：配置空间类型，0-Agent设备配置空间，1-PCI桥配置空间，2-Cardbus桥配置空间。

Cache Line Size：0x0c，读写，记录HOST处理器使用的Cache行长度。PCI总线相关使用会使用到该值，由系统软件进行配置，但系统软件本身不会使用该值，PCI设备运行过程中其硬件逻辑会使用该寄存器；（相关事务如：写并无效总线事务、单行读和多行读总线事务，对于不支持Cache事务的PCI设备来说，可以不用配置该寄存器）

Subsystem ID 和 Subsystem Vendor ID：0x2e，0x2c，只读，与Device ID和Vendor ID类似，但略有不同。如Xilinx的pcie IP核的Vendor ID都是0x0007，Device ID都是0x10ee，此时需要这两个寄存来指明厂商ID和设备ID了，如使用该IP核实现网络适配器，Subsystem Vendor ID可配置为0x8086，Subsystem ID可配置为0x10xx；

Capability Pointer：0x34，只读，存放Capabilities 结构链表的头指针offset，offset相对于配置空间的便宜量，在PCI中范围为[0x40, 0xff]，在PCIe中范围为[0x40, 0xfff]。在一个PCIe 设备中，可能含有多个Capability 结构，这些寄存器组成一个链表。其中每一个Capability结构都有唯一的ID 号（如PMC的ID=0x1，PCIEC=0x10），每一个Capability 寄存器都有一个指针，这个指针指向下一个Capability 结构，从而组成一个单向链表结构，这个链表的最后一个Capability 结构的指针为0。如：

所有基本功能寄存器如下：

Interrupt Line：0x3c，读写，系统软件对PCI设备进行配置时写入，记录了当前PCI设备使用的中断向量号。设备驱动程序通过该寄存器获取该设备使用的是处理器那个中断向量号，并注册中断服务程序。该值由PCI设备与8259A中断控制器的链接关系决定，如果处理器系统中未使用8259A中断控制器管理PCI设备中断，则该寄存器无意义。多数PowerPC不使用8259A中断控制器，即使在X86中也很少使用。所以绝大多数处理器系统并不使用该寄存器。

Interrupt Pin：0x3d，读写，保存PCI设备使用的中断引脚。PCI总线提供了4个中断引脚：INTA#、INTB#、INTC#、INTD#，对应的寄存器值分别是1/2/3/4。如果设备不使用这些中断引脚，向处理器提交中断请求时该寄存器必须为0。PCIe设备并不包含INTA~D#信号，但依然使用该寄存器，PCIe设备使用INTx中断消息报文(INTx Interrupt Signaling)来模拟INTA~D#信号，具体详情后续讨论。

Base Address Register0~5：0x10，读写，简称BAR寄存器，用于保存PCI设备使用的PCI总线域的基地址。PCI设备复位后BAR寄存器存放的是设备需使用的地址空间大小、类型（I/O或MEM）、如果是MEM则是否可预取（“Prefectchable”位是否为1）。

关于预读这里简单介绍，更多知识以后探讨。只有“well-behavior”存储器可预读，包括基于SDRAM、DDR-SDRAM、SRAM的主存储器及一些外部设备。“well-behavior”存储器需满足以下4个特点：

1.读操作不会改变存储器内容。某些读清寄存器则不满足太特点，所以不属于“well-behavior”存储器；

2.多次读操作可合并为一次读操作，如对n、n+4、n+8、n+12地址各一次双字读操作，可合并为对n地址的一次突发读操作（大小为4个双字）；

3.多次写操作可合并为一次写操作，如对n、n+4、n+8、n+12地址各一次双字写操作，可合并为对n地址的一次突发写操作（大小为4个双字）。某些外设这种操作会出问题；

4.多次写操作可合并为一次写操作，如对n、n+1、n+2、n+3地址各一次单字写操作，可合并为对n地址的一次DW写操作。某些外设这种操作会出问题。

读取PCI设备BAR空间长度的方法为往BAR寄存器写0xFFFFFFFF，然后读取BAR寄存器。Linux系统中可调用__pci_read_base函数获取BAR空间长度。

因为BAR寄存器中存放的是PCI总线域的地址，CPU并不能直接使用，需将PCI总线域地址映射为存储器域地址。在PowerPC中需要使用inbound和outbound来实现PCI总线域与存储器域的映射，在ARM和X86中PCI总线域地址和存储器域地址数值上相等(数值虽然相等，但概念不同)。关于PCI总线域与存储器域见存储器域与PCI总线域。在Linux系统中，使用pci_resource_start获取BAR空间在存储器域的物理地址，然后使用ioremap将存物理地址转换为虚拟地址。

#define pci_resource_start(dev, bar)	((dev)->resource[(bar)].start)
#define pci_resource_end(dev, bar)	((dev)->resource[(bar)].end)
#define pci_resource_flags(dev, bar)	((dev)->resource[(bar)].flags)
#define pci_resource_len(dev,bar) \
	((pci_resource_start((dev), (bar)) == 0 &&	\
	  pci_resource_end((dev), (bar)) ==		\
	  pci_resource_start((dev), (bar))) ? 0 :	\
							\
	 (pci_resource_end((dev), (bar)) -		\
	  pci_resource_start((dev), (bar)) + 1))

Command：0x04，读写，PCI设备初始化时该寄存器为0，只能接收配置请求总线事务，无法接收其他任何存储器或I/O请求。系统软件需要合理配置该寄存器后才能访问该设备的存储器或I/O空间。在Linux系统中驱动调用pci_enable_device函数使能寄存器的I/O或Memory Space位，

int pci_enable_device_mem(struct pci_dev *dev) //初始化pcie设备并使用它的内存空间
{
    return pci_enable_device_flags(dev, IORESOURCE_MEM);
}
int pci_enable_device_io(struct pci_dev *dev) //初始化pcie设备并使用它的IO空间
{
    return pci_enable_device_flags(dev, IORESOURCE_IO);
}
int pci_enable_device(struct pci_dev *dev)//初始化pcie设备并使用它的IO空间及内存空间。重复的调用此接口并不会多次初始化设备
{
    return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
}

pci_enable_device_flags -> do_pci_enable_device -> pcibios_enable_device ->通过使能Command寄存器使能MEM或IO，如果Interrupt Pin寄存器不为0则给Interrupt Disable位置0，以打开INTx中断。

Command寄存器定义如下图：

Status：0x06，接大部分位只读，定义如下图：

Latency Timer：该寄存器用来控制PCI设备占用总线的时间。对于多数PCI设备而言，该寄存器的值为32或64，以保证一次突发传输的基本单元为一个Cache行。PCIe设备不使用该寄存器时，必须配置为0。

PCI 桥配置空间

PCI桥作为PCI设备，绝大部分配置空间与PCI设备配置空间相同，以下仅介绍不同之处。如下图为PCI桥配置空间：

PCI桥配置空间仅包含2个BAR寄存器，大多数桥并不包含私有配置空间(此时PCI桥需将BAR寄存器初始化为0)，系统软件无需对PCI桥做任何配置，这也是PCI桥称为透明桥的原因。PCI桥使用2个BAR寄存器的原因为可通过BAR0:1组成一个64位地址空间。

Subordinate Bus Number、Secondary Bus Number、Primary Bus Number：PCI桥可管理其下PCI子树，当前PCI子树中编号最大的PCI总线号存放在Subordinate Bus Number中，当前PCI桥的下游总线的总线号存放在Secondary Bus Number中，所以PCI桥管理的子树的PCI总线号范围为[Secondary Bus Number, Subordinate Bus Number]。

Primary Bus Number存放当前PCI桥的上游总线的总线号。

这三个寄存器在初始化时必须为0，系统软件根据是否为0判断桥是否被配置过。

Secondary Latency Timer：管理PCI桥发往下游总线的超时机制。

I/O Limit 、I/O Base、Memory Limit、Memory Base：存放子树中所有设备使用的I/O或MEM地址空间集合的基地址及大小。PCI规定MEM的这个空间至少为1MB。

Prefetchable Memory Limit、Prefetchable Memory Base：存放子树中所有设备使用的可预取MEM空间的基地址及大小。

Bridge Control Register：用来管理下游总线，位定义如下：

Secondary Bus Reset：bit6，可读写，=1 通过RST#信号线复位下游总线上的所有设备。通常情况下下游总线的所有PCI设备的RST#信号线都要连接到当前PCI桥上，而不能直接连接到HOST主桥上

Primary Discard Timer：bit8，用于Delayed传输方式。

Secondary Discard Timer：bit9，用于Delayed传输方式。

PCI 置空间获取

lspci

-x 以16进制显示配置空间的前64字节，或者CardBus桥的前128字节。

-xxx 以16进制显示整个PCI配置空间（256字节）。

-xxxx 以16进制显示整个PCI-E配置空间（4096字节）。


root@firefly:~# lspci -s 0000:01:00.0 -xx
0000:01:00.0 SATA controller: Marvell Technology Group Ltd. 88SE9230 PCIe SATA 6Gb/s Controller (rev 11)
00: 4b 1b 30 92 07 04 10 00 11 01 06 01 00 00 00 00
10: 21 00 10 f0 31 00 10 f0 29 00 10 f0 35 00 10 f0
20: 01 00 10 f0 00 00 24 f0 00 00 00 00 4b 1b 30 92
30: 01 00 20 f0 40 00 00 00 00 00 00 00 86 01 00 00

root@firefly:~# lspci -s 0000:01:00.0 -xxx
0000:01:00.0 SATA controller: Marvell Technology Group Ltd. 88SE9230 PCIe SATA 6Gb/s Controller (rev 11)
00: 4b 1b 30 92 07 04 10 00 11 01 06 01 00 00 00 00
10: 21 00 10 f0 31 00 10 f0 29 00 10 f0 35 00 10 f0
20: 01 00 10 f0 00 00 24 f0 00 00 00 00 4b 1b 30 92
30: 01 00 20 f0 40 00 00 00 00 00 00 00 86 01 00 00
40: 01 50 03 40 00 00 00 00 00 00 00 00 00 00 00 00
50: 05 70 01 00 40 00 67 fe 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 10 e0 12 00 02 87 00 00 10 20 00 00 22 3c 03 00
80: 40 00 22 10 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 12 00 00 00 48 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

root@firefly:~# lspci -s 0000:01:00.0 -xxxx
0000:01:00.0 SATA controller: Marvell Technology Group Ltd. 88SE9230 PCIe SATA 6Gb/s Controller (rev 11)
00: 4b 1b 30 92 07 04 10 00 11 01 06 01 00 00 00 00
10: 21 00 10 f0 31 00 10 f0 29 00 10 f0 35 00 10 f0
20: 01 00 10 f0 00 00 24 f0 00 00 00 00 4b 1b 30 92
30: 01 00 20 f0 40 00 00 00 00 00 00 00 86 01 00 00
40: 01 50 03 40 00 00 00 00 00 00 00 00 00 00 00 00
50: 05 70 01 00 40 00 67 fe 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 10 e0 12 00 02 87 00 00 10 20 00 00 22 3c 03 00
80: 40 00 22 10 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 12 00 00 00 48 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
100: 01 00 01 00 00 00 00 00 00 00 00 00 30 20 06 00
110: 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00
120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
250: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
270: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
290: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
2a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
2b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
2c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
2d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
2e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
2f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
310: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
320: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
330: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
340: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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